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DC综合时遇到的违例应该怎么修改?

时间:10-02 整理:3721RD 点击:
我在给一个设计做综合的时候,系统的工作时钟的设定如下:create_clock -period $clk_100 -name clk [get_ports CLK_100M]
set_clock_latency -source 0.0 clk
set_clock_transition 0.3 clk
set_clock_uncertainty 1.0 clk
set_ideal_network [get_ports CLK_100M]
因为觉得在DC分析时序的时候network_latency在AT和RT路径中都进行了计算,所以就没有设定,然后uncertainty设定是按照周期十分之进行设定的。DRC的设定如下:
set_max_fanout 32 $top_design
set_max_transition3 [current_design]
set_max_capacitance 7 [current_design]

DC综合之后出现了setup的嗜血违例,时序报告如下:
PointFanoutCapTransIncrPath
----------------------------------------------------------------------------------------------
clock clk (rise edge)0.000.00
clock network delay (ideal)0.000.00
convolution/TDATA_REG_3_reg_51_/CK (FFDSHD4X)0.300.00 #0.00 r
convolution/TDATA_REG_3_reg_51_/QN (FFDSHD4X)0.190.410.41 f
convolution/TDATA_REG_3[51] (net)20.050.000.41 f
convolution/U449/A (BUFHD20X)0.190.000.41 f
convolution/U449/Z (BUFHD20X)0.110.200.61 f
convolution/n8951 (net)80.150.000.61 f
convolution/DP_OP_29844J1_124_6330_U13487/A (XOR2HD2X)0.110.000.62 f
convolution/DP_OP_29844J1_124_6330_U13487/Z (XOR2HD2X)0.190.270.88 r
convolution/DP_OP_29844J1_124_6330_n21746 (net)
10.030.000.88 r
convolution/DP_OP_29844J1_124_6330_U13486/A (NAND2HD4X)0.190.000.88 r
convolution/DP_OP_29844J1_124_6330_U13486/Z (NAND2HD4X)0.140.090.97 f
convolution/DP_OP_29844J1_124_6330_n21750 (net)
10.030.000.97 f
convolution/U21239/A (BUFHD20X)0.140.000.97 f
convolution/U21239/Z (BUFHD20X)0.130.201.17 f
convolution/n9395 (net)100.200.001.17 f
convolution/DP_OP_29844J1_124_6330_U13413/BN (OAI21B2HD1X)0.130.001.17 f
convolution/DP_OP_29844J1_124_6330_U13413/Z (OAI21B2HD1X)0.250.261.44 f
convolution/DP_OP_29844J1_124_6330_n21673 (net)
10.020.001.44 f
convolution/U17797/B (FAHHD1X)0.250.001.44 f
convolution/U17797/CO (FAHHD1X)0.220.431.86 f
convolution/DP_OP_29844J1_124_6330_n5908 (net)
10.020.001.86 f
convolution/U25013/A (FAHHD2X)0.220.001.86 f
convolution/U25013/CO (FAHHD2X)0.180.482.34 f
convolution/DP_OP_29844J1_124_6330_n4304 (net)
10.030.002.34 f
convolution/U25701/B (FAHHD2X)0.180.002.34 f
convolution/U25701/S (FAHHD2X)0.180.382.72 f
convolution/DP_OP_29844J1_124_6330_n2923 (net)
10.030.002.72 f
convolution/U9214/B (FAHHD4X)0.180.002.72 f
convolution/U9214/S (FAHHD4X)0.230.453.17 f
convolution/DP_OP_29844J1_124_6330_n2889 (net)
30.080.003.17 f
convolution/intadd_60_U6/B (NOR2HD4X)0.230.003.17 f
convolution/intadd_60_U6/Z (NOR2HD4X)0.210.123.29 r
convolution/intadd_60_n6 (net)10.030.003.29 r
convolution/U9394/A (INVHD4X)0.210.003.29 r
convolution/U9394/Z (INVHD4X)0.090.053.35 f
convolution/intadd_60_n26 (net)10.030.003.35 f
convolution/intadd_60_U4/B (NAND2HD4X)0.090.003.35 f
convolution/intadd_60_U4/Z (NAND2HD4X)0.150.073.41 r
convolution/intadd_60_n1 (net)10.020.003.41 r
convolution/intadd_60_U2/A (XOR2HD4X)0.150.003.41 r
convolution/intadd_60_U2/Z (XOR2HD4X)0.110.213.63 r
convolution/DP_OP_29844J1_124_6330_n2749 (net)
10.020.003.63 r
convolution/U14865/CI (FAHHD2X)0.110.003.63 r
convolution/U14865/S (FAHHD2X)0.130.293.92 f
convolution/DP_OP_29844J1_124_6330_n2699 (net)
10.020.003.92 f
convolution/U25320/CI (FAHHD2X)0.130.003.92 f
convolution/U25320/CO (FAHHD2X)0.140.254.16 f
convolution/DP_OP_29844J1_124_6330_n2644 (net)
10.020.004.16 f
convolution/U15820/A (FAHHD4X)0.140.004.16 f
convolution/U15820/S (FAHHD4X)0.190.504.66 f
convolution/DP_OP_29844J1_124_6330_n1759 (net)
20.060.004.66 f
convolution/U9611/A (INVHD4X)0.190.004.66 f
convolution/U9611/Z (INVHD4X)0.130.084.74 r
convolution/n3469 (net)10.030.004.74 r
convolution/U9612/B (NAND2HD4X)0.130.004.74 r
convolution/U9612/Z (NAND2HD4X)0.160.094.84 f
convolution/intadd_5_n7 (net)20.040.004.84 f
convolution/intadd_5_U12/B (NAND2HD4X)0.160.004.84 f
convolution/intadd_5_U12/Z (NAND2HD4X)0.140.084.91 r
convolution/intadd_5_n2 (net)10.020.004.91 r
convolution/intadd_5_U8/A (XNOR2HD4X)0.140.004.91 r
convolution/intadd_5_U8/Z (XNOR2HD4X)0.110.215.12 f
convolution/DP_OP_29844J1_124_6330_n1753 (net)
10.020.005.12 f
convolution/U17224/A (FAHHD2X)0.110.005.12 f
convolution/U17224/CO (FAHHD2X)0.140.425.54 f
convolution/DP_OP_29844J1_124_6330_n1734 (net)
10.020.005.54 f
convolution/U17136/A (FAHHD2X)0.140.005.54 f
convolution/U17136/CO (FAHHD2X)0.140.425.96 f
convolution/DP_OP_29844J1_124_6330_n980 (net)
10.020.005.96 f
convolution/U25284/A (FAHHD2X)0.140.005.96 f
convolution/U25284/CO (FAHHD2X)0.130.416.38 f
convolution/DP_OP_29844J1_124_6330_n600 (net)
10.020.006.38 f
convolution/U23554/CI (FAHHD2X)0.130.006.38 f
convolution/U23554/S (FAHHD2X)0.160.316.68 r
convolution/DP_OP_29844J1_124_6330_n412 (net)
10.020.006.68 r
convolution/U9408/CI (FAHHD4X)0.160.006.68 r
convolution/U9408/S (FAHHD4X)0.190.387.06 f
convolution/DP_OP_29844J1_124_6330_n410 (net)
20.060.007.06 f
convolution/U9626/A (INVHD4X)0.190.007.06 f
convolution/U9626/Z (INVHD4X)0.130.087.14 r
convolution/n3479 (net)10.030.007.14 r
convolution/U9628/B (NAND2HD4X)0.130.007.15 r
convolution/U9628/Z (NAND2HD4X)0.170.107.24 f
convolution/intadd_40_n26 (net)20.050.007.24 f
convolution/intadd_40_U4/B (NAND2HD4X)0.170.007.25 f
convolution/intadd_40_U4/Z (NAND2HD4X)0.210.117.35 r
convolution/intadd_40_n1 (net)20.040.007.35 r
convolution/U9792/A (XNOR2HD4X)0.210.007.36 r
convolution/U9792/Z (XNOR2HD4X)0.150.257.61 f
convolution/DP_OP_29844J1_124_6330_n408 (net)
20.040.007.61 f
convolution/DP_OP_29844J1_124_6330_U119/B (NOR2HD4X)0.150.007.61 f
convolution/DP_OP_29844J1_124_6330_U119/Z (NOR2HD4X)0.210.127.72 r
convolution/DP_OP_29844J1_124_6330_n113 (net)
10.030.007.72 r
convolution/DP_OP_29844J1_124_6330_U105/B (NOR2HD4X)0.210.007.72 r
convolution/DP_OP_29844J1_124_6330_U105/Z (NOR2HD4X)0.160.097.81 f
convolution/DP_OP_29844J1_124_6330_n106 (net)
20.050.007.81 f
convolution/DP_OP_29844J1_124_6330_U104/A (AOI21HD4X)0.160.007.81 f
convolution/DP_OP_29844J1_124_6330_U104/Z (AOI21HD4X)0.240.167.98 r
convolution/DP_OP_29844J1_124_6330_n105 (net)
10.030.007.98 r
convolution/U2732/C (OAI21HD4X)0.240.007.98 r
convolution/U2732/Z (OAI21HD4X)0.190.138.10 f
convolution/DP_OP_29844J1_124_6330_n1 (net)
10.030.008.10 f
convolution/U22361/A (BUFHD20X)0.190.008.10 f
convolution/U22361/Z (BUFHD20X)0.150.238.33 f
convolution/n10204 (net)80.270.008.33 f
convolution/DP_OP_29844J1_124_6330_U50/B (AOI21HD4X)0.150.008.33 f
convolution/DP_OP_29844J1_124_6330_U50/Z (AOI21HD4X)0.220.138.46 r
convolution/DP_OP_29844J1_124_6330_n63 (net)
10.020.008.46 r
convolution/DP_OP_29844J1_124_6330_U29/A (XOR2HD4X)0.220.008.46 r
convolution/DP_OP_29844J1_124_6330_U29/Z (XOR2HD4X)0.210.318.77 f
convolution/N6164 (net)30.090.008.77 f
convolution/U29713/A (INVHD4X)0.210.008.77 f
convolution/U29713/Z (INVHD4X)0.170.118.88 r
convolution/n48705 (net)20.040.008.88 r
convolution/U7608/B (NOR2HD4X)0.170.008.88 r
convolution/U7608/Z (NOR2HD4X)0.110.068.94 f
convolution/n18102 (net)10.030.008.94 f
convolution/U20461/A (BUFHD20X)0.110.008.94 f
convolution/U20461/Z (BUFHD20X)0.130.209.14 f
convolution/n20592 (net)110.200.009.14 f
convolution/U28799/A (INVHD20X)0.130.009.14 f
convolution/U28799/Z (INVHD20X)0.210.329.46 r
convolution/n20589 (net)130.320.009.46 r
convolution/U2388/A (MUXI2HD1X)0.210.009.46 r
convolution/U2388/Z (MUXI2HD1X)0.160.159.61 f
convolution/n26767 (net)10.010.009.61 f
convolution/SumReg_reg_177__23_/D (FFDQRHDLX)0.160.009.61 f
data arrival time9.61
clock clk (rise edge)10.0010.00
clock network delay (ideal)0.0010.00
clock uncertainty-1.009.00
convolution/SumReg_reg_177__23_/CK (FFDQRHDLX)0.009.00 r
library setup time-0.168.84
data required time8.84
----------------------------------------------------------------------------------------------
data required time8.84
data arrival time-9.61
----------------------------------------------------------------------------------------------
slack (VIOLATED)-0.77

我有几点不是很清楚:
1)DC综合的时候,是不是应该用原来周期的70%进行综合,为了使ICC和PT更容易通过
2)DC中uncertainty的指定,需不需要分开setup,和hold,因为我发现统一指定的时候,我想设定的大一点多留一点margin,就会出现hold的违例可能变大。
3)DC中设定了DRC,那么报出的max_capacitance和max_transition的违例用不用考虑,需要修正吗
4)DC中报出的这个路径上的违例,我看了一下基本都是组合逻辑的延时,是不是要修改代码来修正时序。还是可以通过修正DRC的设定能修正,因为我看了一下,里面插入的buffer和inv的延时大约有1.4左右的延时。
对DC的理解不是很到位,请教一下各位前辈,我做的约束的想法是不是有不对的地方。谢谢了。

个人一点建议:
1. DC综合时一般会有过约束,就是你说的“原来周期的70%”,一般不同的工艺节点过约束的值是不同的,因为综合之后的网表没有位置的概念,将来做布局布线后会吃掉这些过约束
2. uncertainty应该要分开setup和hold, 一般给setup和hold的margin是不同的
3. DRC中transition一般来自.lib的库文件,capacitance一般来自经验值,有一些为例没关系的,后端会修复这些违例
4. 看上去这条路径没有完全优化,可以找一下同一个时钟域下其他路径情况,是否有比较严重的违例,因为DC优化是按照group(一般一个时钟域就是一个group)来的,如果遇到无法优化成match约束的情况,一般不会继续优化同一个group的其他路径。如果没有严重的违例,可以考虑经这条路径单独设为一个group,再不行的话估计要改RTL了。

谢谢啊。我想再请教一点,关于max_transition和max_capacitance的值的设定。max_transition是直接按照.lib库里的默认值,不需要约束的紧一些吗?库里的默认值是3.6,会不会太大了?

max_transition直接按照lib里面的设置就成,只要没有什么特别的违例,后端会修复的

不同cell的max transition设一样吗

不同的cell,max transition是一样的,但是不同的库max transition是不同的,你可以查一下,找个最小值

多谢二楼,学习啦

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