有没有人在做PR报timig的时候遇到过TA-152这个error？
时间：10-02
整理：3721RD
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error的描述是这个样子的：
**ERROR: (TA-152):A latency path from the 'Fall' edge of the master clockat source pin clk' to the 'Rise' edge of generated clock 'gen_clk' at pin 'gen_clk' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'gen_clk'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
为什么会差生这个error?
这个error对timing有什么影响?
对cts的结果会不会又差?
该怎么解决他?
欢迎大家来讨论。
**ERROR: (TA-152):A latency path from the 'Fall' edge of the master clockat source pin clk' to the 'Rise' edge of generated clock 'gen_clk' at pin 'gen_clk' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'gen_clk'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
为什么会差生这个error?
这个error对timing有什么影响?
对cts的结果会不会又差?
该怎么解决他?
欢迎大家来讨论。
没有generate_clock?还是在贴回sdc文件的时候出了问题吧?编辑的sdc文件有问题吧，需要改动
sdc有问题吧，边沿没设置对，对cts的影响看你怎么做的cts
确实是SDC的问题，generate clock的设置不对，现在正在试看看对CTS及以后的影响
就是正常的用工具长tree，这样子会有什么影响?