同一个master clock 下的generated clk 不能设成异步?
时间:10-02
整理:3721RD
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master clock 下的generated clk 设成异步,gca检查会报错,但他们之间的确是异步的,这个问题怎么解决?
Consider a scenario where two generated clocks with the same master clock are declared asynchronous:
create_clock -period 4 clk1
create_generated_clock -source clk1 -divide_by 2 clk2
create_generated_clock -source clk1 -divide_by 4 clk3
set_clock_groups -asynchronous -group {clk2} -group {clk3}
Consider a scenario where two generated clocks with the same master clock are declared asynchronous:
create_clock -period 4 clk1
create_generated_clock -source clk1 -divide_by 2 clk2
create_generated_clock -source clk1 -divide_by 4 clk3
set_clock_groups -asynchronous -group {clk2} -group {clk3}
以实际为准,GCA只是辅助工具
同源的clockdefault是同步的,设false path好了