有关DC综合时序报告中的问题

给出个报告来看看吧。

****************************************
Report : timing
-path full
-delay max
-max_paths 1
-sort_by group
Design : pic16_top
Version: X-2005.09-SP2
Date: Tue Dec 29 15:20:25 2015
****************************************
Operating Conditions: TYPICALLibrary: smic25_tt
Wire Load Model Mode: segmented
Startpoint: portB_in[1]
(input port clocked by clock)
Endpoint: f_out[1] (output port clocked by clock)
Path Group: clock
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
reg_generalreference_area_1000000
smic25_tt
pic16_topreference_area_1000000
smic25_tt
reg_topreference_area_1000000
smic25_tt
reg_mux_freference_area_20000smic25_tt
mux_alu_breference_area_20000smic25_tt
mux_alu_areference_area_20000smic25_tt
alu_topreference_area_20000smic25_tt
program_counterreference_area_20000smic25_tt
PointIncrPath
--------------------------------------------------------------------------
clock clock (rise edge)0.000.00
clock network delay (ideal)0.000.00
input external delay9.009.00 f
portB_in[1] (in)0.009.00 f
u_reg_top/portB_in[1] (reg_top)0.009.00 f
u_reg_top/u_reg_general/portB_in[1] (reg_general)0.009.00 f
u_reg_top/u_reg_general/U442/Z (AOI222HD2X)0.579.57 r
u_reg_top/u_reg_general/U8/Z (NAND4HD2X)0.199.76 f
u_reg_top/u_reg_general/f_out[1] (reg_general)0.009.76 f
u_reg_top/f_out[1] (reg_top)0.009.76 f
f_out[1] (out)0.009.76 f
data arrival time9.76
clock clock (rise edge)20.0020.00
clock network delay (ideal)0.0020.00
output external delay-9.0011.00
data required time11.00
--------------------------------------------------------------------------
data required time11.00
data arrival time-9.76
--------------------------------------------------------------------------
slack (MET)1.24
另外有些有library的延时，这项延时是什么情况下出现的啊?

那些延迟为0的，比如说你的top的输入portB直接穿到底层模块，相当于直接连过去没有逻辑，这些是0，你这个是输入到输出的path，里面只有组合逻辑没有寄存器，library的延迟，你看看应该是library setup time，是说library中寄存器的建立时间