verilog代码综合问题

module datapath( ctrl, constant, data, vcnz, rst_n, clk);
input [25:0] ctrl;
input [15:0] constant;
input [15:0] data;
input rst_n,clk;
output reg [3:0] vcnz;
wire [3:0] DA = ctrl[25:22];
wire [3:0] AA = ctrl[21:18];
wire [3:0] BA = ctrl[17:14];
wire MB = ctrl[13];
wire [3:0] FS = ctrl[12:9];
wire [2:0] SS = ctrl[8:6];
wire [3:0] SA = ctrl[5:2];
wire MD = ctrl[1];
wire RW = ctrl[0];
reg [15:0] A_data;
reg [15:0] B_data;
reg [15:0] B_Mux_out;
reg [15:0] shifter_out;
reg [16:0] func_out;
reg [15:0] D_data;
reg [15:0] R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15;

always@(posedge clk)
begin
if(rst_n == 0)
begin
R0=16'b0000000000000000;
R1=16'b0000000000000000;
R2=16'b0000000000000000;
R3=16'b0000000000000000;
R4=16'b0000000000000000;
R5=16'b0000000000000000;
R6=16'b0000000000000000;
R7=16'b0000000000000000;
R8=16'b0000000000000000;
R9=16'b0000000000000000;
R10=16'b0000000000000000;
R11=16'b0000000000000000;
R12=16'b0000000000000000;
R13=16'b0000000000000000;
R14=16'b0000000000000000;
R15=16'b0000000000000000;
end
else
begin

end
end

always @(posedge clk)
begin
case(AA)
4'b0000:A_data = R0;
4'b0001:A_data = R1;
4'b0010:A_data = R2;
4'b0011:A_data = R3;
4'b0100:A_data = R4;
4'b0101:A_data = R5;
4'b0110:A_data = R6;
4'b0111:A_data = R7;
4'b1000:A_data = R8;
4'b1001:A_data = R9;
4'b1010:A_data = R10;
4'b1011:A_data = R11;
4'b1100:A_data = R12;
4'b1101:A_data = R13;
4'b1110:A_data = R14;
4'b1111:A_data = R15;
default:;
endcase

case(BA)
4'b0000:B_data = R0;
4'b0001:B_data = R1;
4'b0010:B_data = R2;
4'b0011:B_data = R3;
4'b0100:B_data = R4;
4'b0101:B_data = R5;
4'b0110:B_data = R6;
4'b0111:B_data = R7;
4'b1000:B_data = R8;
4'b1001:B_data = R9;
4'b1010:B_data = R10;
4'b1011:B_data = R11;
4'b1100:B_data = R12;
4'b1101:B_data = R13;
4'b1110:B_data = R14;
4'b1111:B_data = R15;
default:;
endcase

if(RW == 1)
begin
case(DA)
4'b0000:R0 = D_data;
4'b0001:R1 = D_data;
4'b0010:R2 = D_data;
4'b0011:R3 = D_data;
4'b0100:R4 = D_data;
4'b0101:R5 = D_data;
4'b0110:R6 = D_data;
4'b0111:R7 = D_data;
4'b1000:R8 = D_data;
4'b1001:R9 = D_data;
4'b1010:R10 = D_data;
4'b1011:R11 = D_data;
4'b1100:R12 = D_data;
4'b1101:R13 = D_data;
4'b1110:R14 = D_data;
4'b1111:R15 = D_data;
default:;
endcase
end
else
begin

end
end
always @(posedge clk)
begin
case(MB)
1'b1:B_Mux_out = constant;
1'b0:B_Mux_out = B_data;
endcase
end

always @(posedge clk)
begin

if(SA ！= 0)

begin
case(SS)
3'b000:
shifter_out = B_Mux_out >>SA;
3'b001:
shifter_out = B_Mux_out <<SA;
3'b010:shifter_out = B_Mux_out >>SA|B_Mux_out <<(5'd16-SA);
3'b011:shifter_out = B_Mux_out <<SA|B_Mux_out >>(5'd16-SA);
3'b100:
shifter_out = B_Mux_out >>>SA;
default:;
endcase
end
else begin
shifter_out = B_Mux_out;
end

end
always @(posedge clk)
begin
vcnz = 0;
case(FS)
4'b0000:func_out = A_data;
4'b0001:func_out = A_data + 1;
4'b0010:func_out = A_data + shifter_out;
4'b0011:func_out = A_data + shifter_out + 1;
4'b0100:func_out = A_data + ~shifter_out;
4'b0101:func_out = A_data + ~shifter_out + 1;
4'b0110:func_out = A_data - 1;
4'b0111:func_out = A_data;
4'b1000:func_out = A_data&shifter_out;
4'b1001:func_out = A_data|shifter_out;
4'b1010:func_out = A_data^shifter_out;
4'b1011:func_out = ~A_data;
4'b1100:func_out = shifter_out;
default:;
endcase
vcnz[2] = func_out[16];
vcnz[1] = func_out[15]==1'b1 ? 1'b1 : 1'b0;
vcnz[0] = func_out[15:0]==16'b0 ? 1'b1 : 1'b0;
end
always @(posedge clk)
begin
case(MD)
1：D_data = data;
0：D_data = func_out[15:0];
default:;
endcase
end
endmodule


上边是代码
是一个datapath
综合的时候提示
DEFAULT branch of CASE statement cannot be reached.
Warning:/users/course/2015F/cs4125/dsd31/hw4/datapath2.v:54: Net R14[0] or a directly connected net may be driven by more than one process or block. (ELAB-405)

Error:/users/course/2015F/cs4125/dsd31/hw4/datapath2.v:54: Net 'R0[15]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366)
对于定义的所有的寄存器都有报错
还有出现这种东西
Statistics for case statements in always block at line 125 in file
'/users/course/2015F/cs4125/dsd31/hw4/datapath2.v'
===============================================
|Line|full/ parallel|
===============================================
|127|auto/auto|
===============================================
不确定是不是正常的
新手求大神指教，在线等，急

你这代码写得也太随意了。
只说一点：你的R0在复位的always块里面赋值了一遍，然后case（DA）里面又赋值了一遍，这就造成了多驱动的错误。

这代码，
楼上正解

OK，已经解决了，新人第一次写，谢谢两位了