error: $width( negedge CK &&& (flag == 1):3602089 ps

请问我是做post-sim的时候modelsim报如下的错误，该如何解决啊，谢谢：
# ** Error: D:/WORK/1505/Post_sim/tsmc25_new.v(5731): $width( negedge CK &&& (flag == 1):3602089 ps, :3602320 ps, 523 ps );
#Time: 3602320 psIteration: 0Instance: /tb/U_IT1505_1/U_PWM/counter_reg_11_
提示说是CK下降沿的长度不够吗，不太理解哦，CK是我外部给的CLOCK。纠结啊～～
我指点到仿真库tsmc25_new.v里的5731行为：
`timescale 1ns/1ps
`celldefine
module DFFRX1 (Q, QN, D, CK, RN);
output Q, QN;
inputD, CK, RN;
reg NOTIFIER;
supply1 xSN;
bufXX0 (xRN, RN);
bufIC (clk, CK);
udp_dff I0 (n0, D, clk, xRN, xSN, NOTIFIER);
andI4 (flag, xRN, xSN);
bufI1 (Q, n0);
notI2 (QN, n0);
specify
specparam
tplh$RN$Q= 1.0,
tphl$RN$Q= 1.0,
tplh$RN$QN= 1.0,
tphl$RN$QN= 1.0,
tplh$CK$Q = 1.0,
tphl$CK$Q = 1.0,
tplh$CK$QN = 1.0,
tphl$CK$QN = 1.0,
tsetup$D$CK = 1.0,
thold$D$CK = 0.5,
tsetup$RN$CK= 1.0,
thold$RN$CK= 0.5,
tminpwl$RN= 1.0,
tminpwl$CK= 1.0,
tminpwh$CK= 1.0;
if (flag)
(posedge CK *> (Q +: D)) = (tplh$CK$Q,tphl$CK$Q);
if (flag)
(posedge CK *> (QN -: D)) = (tplh$CK$QN,tphl$CK$QN);
$setuphold(posedge CK &&& (flag == 1), posedge D, tsetup$D$CK, thold$D$CK, NOTIFIER);
$setuphold(posedge CK &&& (flag == 1), negedge D, tsetup$D$CK, thold$D$CK, NOTIFIER);
(negedge RN *> (Q +: 1'b0)) = (tphl$RN$Q);
(negedge RN *> (QN -: 1'b0)) = (tplh$RN$QN);
$setuphold(posedge CK, posedge RN, tsetup$RN$CK, thold$RN$CK, NOTIFIER);
$width(negedge RN, tminpwl$RN, 0, NOTIFIER);
$width(negedge CK &&& (flag == 1), tminpwl$CK, 0, NOTIFIER);
$width(posedge CK &&& (flag == 1), tminpwh$CK, 0, NOTIFIER);
endspecify
endmodule // DFFRX1
`endcelldefine
请大侠帮帮忙，谢谢～～～～

可能是频率太高了，min_pulse_width不够

谢谢你的热心回复，我仔细看了下，发现是前面有hold timing的问题，然后影响到该FF，所以发生了width。 当没有hold timing的时候，该error也会消失～～～～
谢谢

我放的网表也产生了这个问题。我把时钟稍微降低一点，就不会有这种问题了。