illegal 'timescale for module反标后仿真

求助各位前辈，在反标sdf后进行vcs仿真，提示error:illegal 'timescale for module,module"AN2D0" has 'timescale but previous module do not，请问这个是什么意思呢?怎么解决呢?谢谢各位啦！

自己顶一个

你看看网表里"AN2D0" 的描述里面有一个timescale，但是你其他的module没有定义timescale

nc里面-override_timescale -timescale 1ns/1ps
就是把原有的timescale全部改写为1ns/1ps
vcs里面应该也可以类似的处理，看一下UG

nc是什么东东?

小编，这个问题解决了没，怎么解决的

solvnet:
Question:
What does VCS"Error-[ITSFM] Illegal `timescale for module" mean?
Answer:
VCS/VCSMX will generate a compile error "Error-[ITSFM] Illegal `timescale for module"
if the first Verilog source file passed to the vcs compile command does not have a
`timescale directive and subsequent Verilog sources do.
To overcome this error, there are 3 things the user can do:
1) Reorder the source files passed to VCS (Refer to solvnet article DOC ID
900543 for information on how timescales are defined and used by simulators).
2) Use the VCS' -timescale=base/precision Verilog compile option
where you specify base and precision. Ex:
% vcs no_timescale.v file_with_timescale.v -timescale=1ns/10ps
-timescale=base/precision will use the timescale provided on the compile
command for the first Verilog file passed to VCS IF there is no explicit
`timescale directive in the first Verilog source file passed.
3) Use VCS' Verilog compile option -override_timescale=base/resolution option.
This will override all timescales (including explicit `timescale directives)
and have VCS use the timecale specified by this option. Ex:
% vcs no_timescale.v file_with_timescale.v -override_timescale=1ns/1ns
If file_with_timescale.v has a `timescale 1ns/10ps directive, this will be
overriden by VCS and VCS will use 1ns/1ns timescale for ALL Verilog modules.