求助！关于DC综合后的时序报告

DC综合之后的时序报告，不知道如何修改 请各位大牛给点意见
Warning: Design 'cascade_top' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Information: Updating design information... (UID-85)
Warning: Design 'cascade_top' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : cascade_top
Version: E-2010.12
Date: Mon Jan5 22:02:17 2015
****************************************
# A fanout number of 1000 was used for high fanout net computations.
Operating Conditions: ss_1v62_125cLibrary: ss_1v62_125c
Wire Load Model Mode: top
Startpoint: clk_enable (input port clocked by clk)
Endpoint: hcic_com/delay_pipeline_reg_0__49_
(rising edge-triggered flip-flop clocked by In_clk2)
Path Group: In_clk2
Path Type: max
PointIncrPath
--------------------------------------------------------------------------
clock clk (rise edge)5850.005850.00
clock network delay (ideal)3.005853.00
input external delay0.015853.01 r
clk_enable (in)0.005853.01 r
hcic_com/clk_enable (Hciccomp)0.005853.01 r
hcic_com/U2006/Y (NAND2X3M)0.075853.08 f
hcic_com/U3500/Y (CLKBUFX12M)0.175853.26 f
hcic_com/U1455/Y (CLKBUFX20M)0.175853.43 f
hcic_com/U275/Y (CLKBUFX24M)0.185853.61 f
hcic_com/U1444/Y (CLKINVX16M)0.075853.68 r
hcic_com/U2111/Y (NAND2X2M)0.075853.75 f
hcic_com/U2105/Y (CLKBUFX4M)0.175853.92 f
hcic_com/U5641/Y (INVX4M)0.075854.00 r
hcic_com/U5643/Y (NAND2X2M)0.065854.06 f
hcic_com/U2097/Y (CLKAND2X2M)0.195854.26 f
hcic_com/U2093/Y (NAND2X2M)0.085854.33 r
hcic_com/U5638/Y (AO22X2M)0.185854.51 r
hcic_com/U67/Y (BUFX2M)0.145854.66 r
hcic_com/U75/Y (CLKINVX3M)0.075854.73 f
hcic_com/U77/Y (NAND2X2M)0.085854.81 r
hcic_com/U74/Y (CLKNAND2X2M)0.095854.90 f
hcic_com/U4731/Y (INVXLM)0.075854.97 r
hcic_com/delay_pipeline_reg_0__49_/D (DFFRQX4M)0.005854.97 r
data arrival time5854.97
clock In_clk2 (rise edge)6240.006240.00
clock network delay (ideal)3.006243.00
clock uncertainty-0.506242.50
hcic_com/delay_pipeline_reg_0__49_/CK (DFFRQX4M)0.006242.50 r
library setup time-0.246242.26
data required time6242.26
--------------------------------------------------------------------------
data required time6242.26
data arrival time-5854.97
--------------------------------------------------------------------------
slack (MET)387.29

Startpoint: clk_enable (input port clocked by clk)
Endpoint: half_band/delay_pipeline_reg_56__43_
(rising edge-triggered flip-flop clocked by In_clk3)
Path Group: In_clk3
Path Type: max
PointIncrPath
--------------------------------------------------------------------------
clock clk (rise edge)12090.0012090.00
clock network delay (ideal)3.0012093.00
input external delay0.0112093.01 r
clk_enable (in)0.0012093.01 r
half_band/clk_enable (Hhb)0.0012093.01 r
half_band/U2989/Y (AND2X12M)0.1512093.16 r
half_band/U17072/Y (BUFX4M)0.1412093.30 r
half_band/U6653/Y (CLKBUFX24M)0.1712093.47 r
half_band/U4566/Y (INVX16M)0.0612093.52 f
half_band/U1549/Y (CLKBUFX20M)0.1512093.68 f
half_band/U2541/Y (INVX14M)0.0712093.75 r
half_band/U1948/Y (CLKBUFX32M)0.1612093.92 r
half_band/U1069/Y (INVX10M)0.0512093.97 f
half_band/U32243/Y (OR2X2M)0.1812094.15 f
half_band/U15087/Y (INVX2M)0.0712094.22 r
half_band/U34069/Y (INVX2M)0.0512094.27 f
half_band/U9643/Y (BUFX6M)0.1512094.42 f
half_band/U2770/Y (CLKBUFX40M)0.1612094.58 f
half_band/U31158/Y (OR2X4M)0.1912094.77 f
half_band/U9178/Y (BUFX8M)0.1512094.92 f
half_band/U26660/Y (OA22X2M)0.2612095.18 f
half_band/U26661/Y (INVXLM)0.0812095.26 r
half_band/U10947/Y (BUFX2M)0.1312095.39 r
half_band/U18607/Y (AO22X2M)0.1812095.57 r
half_band/U444/Y (BUFX2M)0.1412095.71 r
half_band/U641/Y (CLKINVX3M)0.0712095.79 f
half_band/U644/Y (NAND2X2M)0.0812095.87 r
half_band/U640/Y (NAND2X2M)0.0712095.94 f
half_band/U21315/Y (INVXLM)0.0812096.02 r
half_band/delay_pipeline_reg_56__43_/D (DFFRHQX1M)0.0012096.02 r
data arrival time12096.02
clock In_clk3 (rise edge)12480.0012480.00
clock network delay (ideal)3.0012483.00
clock uncertainty-0.5012482.50
half_band/delay_pipeline_reg_56__43_/CK (DFFRHQX1M)0.0012482.50 r
library setup time-0.2012482.30
data required time12482.30
--------------------------------------------------------------------------
data required time12482.30
data arrival time-12096.02
--------------------------------------------------------------------------
slack (MET)386.28

Startpoint: U1/count_3_reg_4_
(rising edge-triggered flip-flop clocked by clk)
Endpoint: U1/count_3_reg_2_
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
PointIncrPath
-----------------------------------------------------------
clock clk (rise edge)0.000.00
clock network delay (ideal)3.003.00
U1/count_3_reg_4_/CK (DFFRHQX8M)0.003.00 r
U1/count_3_reg_4_/Q (DFFRHQX8M)0.283.28 f
U1/U50/Y (CLKBUFX32M)302.83 #306.12 f
U1/U73/Y (OAI2B1X1M)0.24 #306.36 f
U1/U31/Y (DLY1X1M)0.34306.70 f
U1/U39/Y (INVXLM)0.08306.78 r
U1/U30/Y (BUFX2M)0.14306.92 r
U1/U37/Y (BUFX2M)0.14307.06 r
U1/U52/Y (NAND2X2M)0.07307.13 f
U1/U36/Y (CLKNAND2X2M)0.06307.19 r
U1/U44/Y (AND2X2M)0.15307.34 r
U1/count_3_reg_2_/D (DFFRQX2M)0.00307.34 r
data arrival time307.34
clock clk (rise edge)390.00390.00
clock network delay (ideal)3.00393.00
clock uncertainty-0.50392.50
U1/count_3_reg_2_/CK (DFFRQX2M)0.00392.50 r
library setup time-0.25392.25
data required time392.25
-----------------------------------------------------------
data required time392.25
data arrival time-307.34
-----------------------------------------------------------
slack (MET)84.91

1

****************************************
Report : timing
-path full
-delay min
-max_paths 1
Design : cascade_top
Version: E-2010.12
Date: Mon Jan5 22:08:13 2015
****************************************
# A fanout number of 1000 was used for high fanout net computations.
Operating Conditions: ff_1v98_m40cLibrary: ff_1v98_m40c
Wire Load Model Mode: top
Startpoint: clk_enable (input port clocked by clk)
Endpoint: hcic_com/IN_PROCESS_cur_count_reg_0_
(rising edge-triggered flip-flop clocked by In_clk2)
Path Group: In_clk2
Path Type: min
PointIncrPath
--------------------------------------------------------------------------
clock clk (rise edge)6240.006240.00
clock network delay (ideal)3.006243.00
input external delay0.016243.01 r
clk_enable (in)0.006243.01 r
hcic_com/clk_enable (Hciccomp)0.006243.01 r
hcic_com/U106/Y (OA21X2M)0.076243.08 r
hcic_com/U107/Y (INVXLM)0.026243.10 f
hcic_com/IN_PROCESS_cur_count_reg_0_/D (DFFRQX2M)0.006243.10 f
data arrival time6243.10
clock In_clk2 (rise edge)6240.006240.00
clock network delay (ideal)3.006243.00
clock uncertainty0.506243.50
hcic_com/IN_PROCESS_cur_count_reg_0_/CK (DFFRQX2M)0.006243.50 r
library hold time0.026243.52
data required time6243.52
--------------------------------------------------------------------------
data required time6243.52
data arrival time-6243.10
--------------------------------------------------------------------------
slack (VIOLATED)-0.42

Startpoint: clk_enable (input port clocked by clk)
Endpoint: half_band/IN_PROCESS_cur_count_reg_0_
(rising edge-triggered flip-flop clocked by In_clk3)
Path Group: In_clk3
Path Type: min
PointIncrPath
--------------------------------------------------------------------------
clock clk (rise edge)12480.0012480.00
clock network delay (ideal)3.0012483.00
input external delay0.0112483.01 f
clk_enable (in)0.0012483.01 f
half_band/clk_enable (Hhb)0.0012483.01 f
half_band/U21206/Y (OA21X2M)0.1212483.12 f
half_band/IN_PROCESS_cur_count_reg_0_/D (DFFSX4M)0.0012483.12 f
data arrival time12483.12
clock In_clk3 (rise edge)12480.0012480.00
clock network delay (ideal)3.0012483.00
clock uncertainty0.5012483.50
half_band/IN_PROCESS_cur_count_reg_0_/CK (DFFSX4M)0.0012483.50 r
library hold time0.0212483.52
data required time12483.52
--------------------------------------------------------------------------
data required time12483.52
data arrival time-12483.12
--------------------------------------------------------------------------
slack (VIOLATED)-0.39

Startpoint: clk_enable (input port clocked by clk)
Endpoint: cic_filter_delay0_reg_1__6_
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
PointIncrPath
--------------------------------------------------------------------------
clock clk (rise edge)0.000.00
clock network delay (ideal)3.003.00
input external delay0.013.01 f
clk_enable (in)0.003.01 f
U886/Y (NAND2X6M)0.033.04 r
U2896/Y (OAI2BB1X2M)0.023.06 f
cic_filter_delay0_reg_1__6_/D (DFFRQX4M)0.003.06 f
data arrival time3.06
clock clk (rise edge)0.000.00
clock network delay (ideal)3.003.00
clock uncertainty0.503.50
cic_filter_delay0_reg_1__6_/CK (DFFRQX4M)0.003.50 r
library hold time0.023.52
data required time3.52
--------------------------------------------------------------------------
data required time3.52
data arrival time-3.06
--------------------------------------------------------------------------
slack (VIOLATED)-0.46

Hold 的不用管，pr做的。

还想问下这个clk（rise edge）很大是代表什么意思呢

同问

set_max_fanout
buf太多了，时钟还是约束成理想的吧。现在setup都满足了啊，hold,违就违呗，现在看时序意义不大，
rise edge是起点，上沿触发