signoff STA is timing-violation clean, but the post_simulations fails

Evening, everyone, sincerely hoping for your help for the given troubles:
I have done the signoff STA for my design, for which the result shows no timing violation, however, the post simulations fails. and I have reported the timing_path which shows violations during post_simulation, and found no violations in the STA report.
where does this result from?
given below is the detailed info:
A.the post simulation log:
Timing violation in testbench.u_design_1.u_design_top1.u_encodingT.u_tmp.\enc_out_shifter_reg[56]
$setuphold( posedge CK &&& (vcond2 == 1'b1):3189300120, negedge D:3189300120, limits: (10,10) );
B.the STA report for the path above
****************************************
Report : timing
-path_type full
-delay_type min
-max_paths 1
Design : design
Version: E-2010.12-SP3
Date: Tue Sep 20 21:14:28 2011
****************************************

Startpoint: u_design_top1/u_encodingT/u_tmp/enc_out_shifter_reg[56]
(rising edge-triggered flip-flop clocked by encodingT_clk)
Endpoint: u_design_top1/u_encodingT/u_tmp/enc_out_shifter_reg[56]
(rising edge-triggered flip-flop clocked by encodingT_clk)
Path Group: encodingT_clk
Path Type: min
PointIncrPath
------------------------------------------------------------------------------
clock encodingT_clk (rise edge)0.000.00
clock network delay (propagated)2.902.90
u_design_top1/u_encodingT/u_tmp/enc_out_shifter_reg[56]/CK (SDFPNSRBQQB1)
0.002.90 r
u_design_top1/u_encodingT/u_tmp/enc_out_shifter_reg[56]/QB (SDFPNSRBQQB1)
0.57 &3.47 r
u_design_top1/u_encodingT/u_tmp/U64/YN (OAI22D1)0.14 &3.61 f
u_design_top1/u_encodingT/u_tmp/enc_out_shifter_reg[56]/D (SDFPNSRBQQB1)
0.00 &3.61 f
data arrival time3.61
clock encodingT_clk (rise edge)0.000.00
clock network delay (propagated)2.902.90
clock reconvergence pessimism0.002.90
clock uncertainty0.603.50
u_design_top1/u_encodingT/u_tmp/enc_out_shifter_reg[56]/CK (SDFPNSRBQQB1)
3.50 r
library hold time-0.193.31
data required time3.31
------------------------------------------------------------------------------
data required time3.31
data arrival time-3.61
------------------------------------------------------------------------------
slack (MET)0.30

plz help, and thanks in advance.

setup的timing呢?

also no setup violations in the signoff STA report.

what does the post simulation log mean? It indicates a setup or hold violation?

看看具体fail的位置， path，
有时候和slack的余量大小有点关系，比如再增加PR里面的setup、hold的margin， 再run下，
不是>0 就可以保证work的，

谢谢icfb,又看了一下,直接用icc里导出的sdc约束做了一下sta,还是有violation的.
问个其它问题:
依然是CTS的问题,现在芯片是按两种sscenario来做的,一个是function(主时钟48M,里面有多个生成时钟),另一个scenario是test(主时钟16M,
直接将所有DFF串起来,做DFT),如果只做function的话,skew可做到0.3,但是现在是将两个scenario都将cts_mode设成了true,做出来skew
达4.5,问一下,该如何优化一下这个CTS?
谢谢！

一般 cts scenario只能是一个scenario吧，不能是多个，
如果是多个mode下的cts都要做， 那就不用设cts scenario了，
compile_clock_tree -clock XXX一个一个做好了，
然后optimize_clock_tree
缺省不设cts scenario的话， 每个scenario的clock都会做的
也可以以func mode为主， test mode很多路径都是用func的clock tree的

学习了阿,谢谢各位大牛的解答,谢谢

版大。如果是generate clock怎么处理?是不是吧master clock 长好了就好了

缺省啥都不管，他会自动balance的， 如果不好自己再调整