关于clock uncertainty

手册中关于uncertainty的解释如下：
Before clock tree synthesis, clock uncertainty is caused by clock jitter, which is the
variation in the clock edge times of the source clock, as well as clock skew, which is the
difference in clock arrival times resulting from different propagation delays from the chip’s
clock pins to different sequential devices in the chip. After clock tree synthesis, with
propagated latency, the tool separately accounts for uncertainty resulting from different
propagation delays through the clock tree.
我想问的是，CTS不就是为了使clk到达各个寄存器的时刻相同吗，那怎么还会有different propagation delays through the clock tree

clock走的距离不一样当然就会有clock uncertainty，就算距离一样也会有差别

我的理解是：就是因为要平衡时钟树，所以才要加入different propagation delays，让每条path的时钟信号尽量同时到达

clock走的距离（buffer数目）不一样当然就会有clock uncertainty，就算距离一样也会有差别

学习中！

不是 CTS时候确实加入了不同的延迟，使每条path上的延迟相同；但是相同之后每条path上不就是没有 different propagation delay了吗?但是手册上说 CTS之后 每条path上还是会有 different prppagation delay 不知道为什么

CTS的目标是使用各条path的delay都一样，但是因为是不同的path，clk源到各个endpoint的delay会有些微的差异，这就是propagate delay。

因为本身每条path还是有delay的吧，propagate delay是为了平衡每条线路的总时间的。我的理解就是这样了