generated clock设置问题
时间：10-02
整理：3721RD
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Picture shows an example where the clockSYS_CLKis gated by the
output of a flip-flop. Since the output of the flip-flop may not be a constant,
one way to handle this situation is to define a generated clock at the output
of theandcell which is identical to the input clock.
将门控时钟设置成generated clock在STA操作中有什么好处和作用?求大神解答~
output of a flip-flop. Since the output of the flip-flop may not be a constant,
one way to handle this situation is to define a generated clock at the output
of theandcell which is identical to the input clock.
将门控时钟设置成generated clock在STA操作中有什么好处和作用?求大神解答~
1，利于分析UAND1的两个输入端的时序是否满足（若不满足则可能在CORE_CLK上产生glitch）
2，利于分析SYS_CLK和CORE_CLK这两个时钟域之间的path
楼下补充
是不是也可以方便得到源clock的latency