读进rtl代码后,warning,重要吗?
时间:10-02
整理:3721RD
点击:
Warning: In design 'aes_ASIC', input port 'PAD_wb_clk_i' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_rst_i' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_cyc_i' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[5]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[4]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[3]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[2]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[1]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[0]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_dat_i[31]
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_rst_i' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_cyc_i' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[5]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[4]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[3]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[2]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[1]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_adr_i[0]' drives wired logic;
(the port direction may have been specified incorrectly). (LINT-6)
Warning: In design 'aes_ASIC', input port 'PAD_wb_dat_i[31]
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warning求助
我个人认为不重要吧,因为可配置双向IO内部结构的原因。