encounter时发现很多empty module，感觉有问题，请高手帮忙看下

我用一个IBM的库进行的综合，得到了网标，结果用encounter读入时，第一步就不对劲（图形窗口总是一条细线和几个字，没有floorplan）。
encounter提示我如下信息：
Found empty module (ADD_UNS_OP).
Found empty module (\**SEQGEN** ).
Found empty module (GTECH_AND2).
Found empty module (GTECH_OR2).
Found empty module (GTECH_BUF).
Found empty module (SELECT_OP).
Found empty module (GTECH_NOT).
Found empty module (GTECH_OR3).
Found empty module (MULT_UNS_OP).
Found empty module (GTECH_OR4).
Found empty module (GTECH_OR5).
Found empty module (ASHR_UNS_UNS_OP).
Found empty module (SUB_UNS_OP).
Found empty module (LT_UNS_OP).
Found empty module (GT_UNS_OP).
Found empty module (NE_UNS_OP).
Found empty module (EQ_UNS_OP).
感觉以上的东西是GTECH的（Synopsys 里不依赖于工艺的那么一个库）。但是我就不懂，我综合时用的明明是我们自己的库，GTECH 是怎么出现的呢?以下就是我综合的synopsys.setup文件：

# Synopsys Cache Directory

set cache_read "~/local/tmp/synopsys_cache"

set cache_write "~/local/tmp/synopsys_cache"

set search_path ". ~/ASIC/aci/sc-x/synopsys"

set hdlin_translate_off_skip_text TRUE

#------ IBMXXnm library

set link_library "* scx3_cmos9sf_rvt_tt_1p2v_25c.db dw_foundation.sldb"

set target_library "scx3_cmos9sf_rvt_tt_1p2v_25c.db"

set default_schematic_options "-size infinite"

set synthetic_library "dw_foundation.sldb"

set command_log_file "command.log"

set view_command_log_file "view_command.log"

set plot_command "lpr -Plw"

set text_print_command "lpr -Plw"

set hdlin_source_to_gates_mode "high"

set edifin_ground_name "VSS"

set edifin_ground_net_name "VSS"

set edifin_ground_net_property_name "global"

set edifin_ground_net_property_value "VSS"

set edifin_ground_pin_name "VSS"

set edifin_ground_port_name "VSS"

set edifin_netlist_only "true" ……

下面是我跑encounter的时候用到的脚本
global rda_Input
set cwd /homes/grad/ASIC/layout
set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1 }
set rda_Input(ui_netlist) "~/Design/mydeisng/bugate/TopDigital.v"
set rda_Input(ui_netlisttype) {Verilog}
set rda_Input(ui_rtllist) ""
set rda_Input(ui_ilmdir) ""
set rda_Input(ui_ilmlist) ""
set rda_Input(ui_ilmspef) ""
set rda_Input(ui_settop) {1}
set rda_Input(ui_topcell) {TopDigital}
set rda_Input(ui_celllib) ""
set rda_Input(ui_iolib) ""
set rda_Input(ui_areaiolib) ""
set rda_Input(ui_blklib) ""
set rda_Input(ui_kboxlib) ""
set rda_Input(ui_gds_file) ""
set rda_Input(ui_oa_oa2lefversion) {}
set rda_Input(ui_view_definition_file) ""
set rda_Input(ui_timelib,max) ""
set rda_Input(ui_timelib,min) ""
set rda_Input(ui_timelib) "~/ASIC/aci/sc-x/synopsys/scx3_cmos9sf_rvt_tt_1p2v_25c.lib"
set rda_Input(ui_smodDef) ""
set rda_Input(ui_smodData) ""
set rda_Input(ui_locvlib) ""
set rda_Input(ui_dpath) ""
set rda_Input(ui_tech_file) ""
set rda_Input(ui_timingcon_file,full) ""
set rda_Input(ui_latency_file) ""
set rda_Input(ui_scheduling_file) ""
set rda_Input(ui_buf_footprint) {}
set rda_Input(ui_delay_footprint) {}
set rda_Input(ui_inv_footprint) {}
set rda_Input(ui_leffile) "~/ASIC/aci/sc-x/lef/cmos9sf_8lm_2thick_tech.lef ~/ASIC/aci/sc-x/lef/cmos9sfrvt_macros.lef"
set rda_Input(ui_cts_cell_footprint) {}
set rda_Input(ui_cts_cell_list) {}
set rda_Input(ui_core_cntl) {aspect}
set rda_Input(ui_aspect_ratio) {1.0}
set rda_Input(ui_core_util) {0.7}
set rda_Input(ui_core_height) {}
set rda_Input(ui_core_width) {}
set rda_Input(ui_core_to_left) {}
set rda_Input(ui_core_to_right) {}
set rda_Input(ui_core_to_top) {}
set rda_Input(ui_core_to_bottom) {}
set rda_Input(ui_max_io_height) {0}
set rda_Input(ui_row_height) {}
set rda_Input(ui_isHorTrackHalfPitch) {0}
set rda_Input(ui_isVerTrackHalfPitch) {1}
set rda_Input(ui_ioOri) {R0}
set rda_Input(ui_isOrigCenter) {0}
set rda_Input(ui_isVerticalRow) {0}
set rda_Input(ui_exc_net) ""
set rda_Input(ui_delay_limit) {1000}
set rda_Input(ui_net_delay) {1000.0ps}
set rda_Input(ui_net_load) {0.5pf}
set rda_Input(ui_in_tran_delay) {0.0ps}
set rda_Input(ui_captbl_file) ""
set rda_Input(ui_preRoute_cap) {1}
set rda_Input(ui_postRoute_cap) {1}
set rda_Input(ui_postRoute_xcap) {1}
set rda_Input(ui_preRoute_res) {1}
set rda_Input(ui_postRoute_res) {1}
set rda_Input(ui_shr_scale) {1.0}
set rda_Input(ui_rel_c_thresh) {0.03}
set rda_Input(ui_tot_c_thresh) {5.0}
set rda_Input(ui_cpl_c_thresh) {3.0}
set rda_Input(ui_time_unit) {none}
set rda_Input(ui_cap_unit) {}
set rda_Input(ui_oa_reflib) {}
set rda_Input(ui_oa_abstractname) {}
set rda_Input(ui_oa_layoutname) {}
set rda_Input(ui_sigstormlib) ""
set rda_Input(ui_cdb_file,min) ""
set rda_Input(ui_cdb_file,max) ""
set rda_Input(ui_cdb_file) ""
set rda_Input(ui_echo_file,min) ""
set rda_Input(ui_echo_file,max) ""
set rda_Input(ui_echo_file) ""
set rda_Input(ui_xtwf_file) ""
set rda_Input(ui_qxtech_file) ""
set rda_Input(ui_qxlayermap_file) ""
set rda_Input(ui_qxlib_file) ""
set rda_Input(ui_qxconf_file) ""
set rda_Input(ui_pwrnet) {vdd}
set rda_Input(ui_gndnet) {vss}
set rda_Input(flip_first) {1}
set rda_Input(double_back) {1}
set rda_Input(assign_buffer){1}
set rda_Input(use_io_row_flow) {0}
set rda_Input(ui_gen_footprint) {0}
请大侠帮我分析一下是哪里错了?

用特定的standard cell library进行综合，为什么会出现 (ADD_UNS_OP).
(\**SEQGEN** ).(GTECH_AND2).(GTECH_OR2).(GTECH_BUF).(SELECT_OP).
(GTECH_NOT).(GTECH_OR3).(MULT_UNS_OP).(GTECH_OR4).(GTECH_OR5).
(ASHR_UNS_UNS_OP).(SUB_UNS_OP).(LT_UNS_OP).(GT_UNS_OP).(NE_UNS_OP).(EQ_UNS_OP). 这些东西?

求大侠点拨一下，谢谢啊。

netlist 不是 gate level 的

求大侠点拨一下，谢谢啊。

根本没综合好，拜托