DC综合set_clock_gating_check问题
时间：10-02
整理：3721RD
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1. 我在DC综合时,针对命令"set_clock_gating_check"有以下warning,不懂是怎么产生的,又怎么去解决呢?
Warning: No controlling value could be found for the clock gating cell 'q_clk_gen/U3' for the clock pin 'B1'. (TIM-128)
Warning: Gated clock latch is not created for cell 'q_clk_gen/U7'on pin 'B0' in design '***_digital'. (TIM-141)
Warning: A non-unate path in clock network for clock 'CLKIN_in'
Warning: No controlling value could be found for the clock gating cell 'q_clk_gen/U3' for the clock pin 'B1'. (TIM-128)
Warning: Gated clock latch is not created for cell 'q_clk_gen/U7'on pin 'B0' in design '***_digital'. (TIM-141)
Warning: A non-unate path in clock network for clock 'CLKIN_in'
2. create_generated_clock –edges {1 3 5} –source CLK [get_pints foo2]
如何理解下面这句话? 创建生成时钟沿为主时钟的1,3,5沿。如果主时钟周期为30，波形{24 36}，生成时钟周期为60，波形为{24 54}
波形{24 36}是什么意思?
为什么新生成的时钟周期为60?
问题2,已理解,谢谢
问题2已理解,谢谢
问题一，解决了吗?如何解决的?