DC不能生成网表文件。

#set rpt_file "/home/project/spi_syn/log/spi.rpt"
#set design"/home/project/spi_syn/src/spi.v"
#set log_directory "/home/project/spi_syn/log/"
read_file -format verilog {/home/project/spi_syn/src/spi.v}
Loading db file '/eda/synopsys/dc2008_09/libraries/syn/gtech.db'
Loading db file '/eda/synopsys/dc2008_09/libraries/syn/standard.sldb'
Loading link library 'gtech'
Loading verilog file '/home/project/spi_syn/src/spi.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/project/spi_syn/src/spi.v

Statistics for case statements in always block at line 191 in file
'/home/project/spi_syn/src/spi.v'
===============================================
|Line|full/ parallel|
===============================================
|192|auto/auto|
===============================================

Statistics for case statements in always block at line 247 in file
'/home/project/spi_syn/src/spi.v'
===============================================
|Line|full/ parallel|
===============================================
|261|auto/auto|
|298|auto/auto|
===============================================

Inferred memory devices in process
in routine SPI_CORE line 158 in file
'/home/project/spi_syn/src/spi.v'.
===============================================================================
|Register Name|Type| Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|reset_d2n_reg| Flip-flop |1|N| N| N| N| N| N| N|
|reset_dn_reg| Flip-flop |1|N| N| N| N| N| N| N|
|reset_d3n_reg| Flip-flop |1|N| N| N| N| N| N| N|
|rst_sclkp_reg| Flip-flop |1|N| N| N| N| N| N| N|
===============================================================================

Inferred memory devices in process
in routine SPI_CORE line 173 in file
'/home/project/spi_syn/src/spi.v'.
===============================================================================
|Register Name|Type| Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|omux_sel_reg| Flip-flop |2|N| N| N| N| N| N| N|
|data_out_reg| Flip-flop |16|Y| N| N| N| N| N| N|
===============================================================================

Inferred memory devices in process
in routine SPI_CORE line 227 in file
'/home/project/spi_syn/src/spi.v'.
===============================================================================
|Register Name|Type| Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|stat_mat_reg| Flip-flop |1|N| N| N| N| N| N| N|
|clk_cnt_reg| Flip-flop |4|Y| N| N| N| N| N| N|
|spi_st_reg| Flip-flop |3|Y| N| N| N| N| N| N|
|data_in_reg| Flip-flop |14|Y| N| N| N| N| N| N|
|rd_wrn_reg| Flip-flop |1|N| N| N| N| N| N| N|
===============================================================================

Inferred memory devices in process
in routine SPI_CORE line 166 in file
'/home/project/spi_syn/src/spi.v'.
===============================================================================
|Register Name|Type| Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|rst_sclkn_reg| Flip-flop |1|N| N| N| N| N| N| N|
===============================================================================

Inferred memory devices in process
in routine SPI_CORE line 206 in file
'/home/project/spi_syn/src/spi.v'.
===============================================================================
|Register Name|Type| Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|pre_data_wr_reg| Flip-flop |1|N| N| N| N| N| N| N|
|stat_rd_o_reg| Flip-flop |1|N| N| N| N| N| N| N|
|pre_stat_rd_reg| Flip-flop |1|N| N| N| N| N| N| N|
|data_reg_reg| Flip-flop |12|Y| N| N| N| N| N| N|
|data_wr_o_reg| Flip-flop |1|N| N| N| N| N| N| N|
===============================================================================
Presto compilation completed successfully.
Current design is now '/home/project/spi_syn/src/SPI_CORE.db:SPI_CORE'
Loaded 1 design.
Current design is 'SPI_CORE'.
SPI_CORE
read_file -format verilog {/home/project/spi_syn/src/buf_i.v}
Loading verilog file '/home/project/spi_syn/src/buf_i.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Performing 'read' command.
Compiling source file /home/project/spi_syn/src/buf_i.v
Reading with netlist reader (equivalent to -netlist option).
Verilog netlist reader completed successfully.
Current design is now '/home/project/spi_syn/src/PS_IBUF.dbS_IBUF'
Loaded 1 design.
Current design is 'PS_IBUF'.
PS_IBUF
read_file -format verilog {/home/project/spi_syn/src/buf_o.v}
Loading verilog file '/home/project/spi_syn/src/buf_o.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Performing 'read' command.
Compiling source file /home/project/spi_syn/src/buf_o.v
Reading with netlist reader (equivalent to -netlist option).
Verilog netlist reader completed successfully.
Current design is now '/home/project/spi_syn/src/PS_OBUF.dbS_OBUF'
Loaded 1 design.
Current design is 'PS_OBUF'.
PS_OBUF
#report lib cell's information
#report_lib lsi_10k.lib -all
current_design SPI_CORE
Current design is 'SPI_CORE'.
{SPI_CORE}
link

Linking design 'SPI_CORE'
Using the following designs and libraries:
--------------------------------------------------------------------------
* (3 designs)/home/project/spi_syn/src/SPI_CORE.db, etc

1
reset_design
1
#check_design
set auto_wire_load_selection true
true
set_wire_load_mode enclosed
1
#this value should be consistent with target library max_fanout&fanout_load
set_fanout_load 2.0 [all_outputs]
1
set_drive1.0 {SDIN}
1
# clock frequency is set as 10Mhz
set clk_name SCLK
SCLK
create_clock -period 100 -waveform [list 0 50] $clk_name
1
set_clock_latency 2.0 [get_clocks $clk_name]
1
set_clock_uncertainty -setup 1.0[get_clocks $clk_name]
1
set_clock_uncertainty -hold0.5[get_clocks $clk_name]
1
set_clock_transition 0.5[get_clocks $clk_name]
1
set_drive 0 $clk_name
1
set_structure -boolean true -boolean_effort high
1
set_structure -timing true
1
set_fix_multiple_port_nets -all -buffer_constants
1
# PS_ibuf does not exists in target library?
#set_driving_cell -lib_cell PS_IBUF -pin Z [all_inputs]
#set_driving_cell -lib_cell PS_IBUF{stat_i[0]}
#set_driving_cell -lib_cell reset_n_buf -pin Z {reset_n_i}
source /home/project/spi_syn/script/timing.tcl
set_load 1.0 DATA
1
set_load 1.0 DATA_WR
1
set_load 1.0 SDOUT
1
#define design constraints
set_input_delay60-clock $clk_name { RESET_N }
1
set_input_delay60-clock $clk_name { CS_N}
1
set_input_delay60-clock $clk_name { SDIN}
1
set_input_delay60-clock $clk_name { ADDR}
1
#set_input_delay60-clock $clk_name { ADDR[11]}
set_input_delay65-clock $clk_name { SDINIT}
1
set_input_delay65-clock $clk_name { BPIN}
1
set_input_delay65-clock $clk_name { STATUS}
1
set_input_delay65-clock $clk_name { INTRPT}
1
set_output_delay 70-clock $clk_name { STAT_RD DATA DATA_WR SDOUT}
1
check_timing
Information: Updating design information... (UID-85)

Information: Checking generated_clocks...

Information: Checking loops...

Information: Checking no_input_delay...

Information: Checking unconstrained_endpoints...

Information: Checking pulse_clock_cell_type...
1
#set_max_delay 75 -to {SDOUT}
set_max_area 0
1
set command_log_file"./transcript.log"
./transcript.log
set view_command_log_file "./view_command.log"
./view_command.log
#report_timing -from SDIN -to SDOUT
#report_design
report_area

****************************************
Report : area
Design : SPI_CORE
Version: B-2008.09
Date: Tue May 20 10:00:53 2014
****************************************

Library(s) Used:

gtech (File: /eda/synopsys/dc2008_09/libraries/syn/gtech.db)

Number of ports:53
Number of nets:501
Number of cells:343
Number of references:27

Combinational area:0.000000
Noncombinational area:0.000000
Net Interconnect area:undefined(No wire load specified)

Total cell area:0.000000
Total area:undefined

Information: This design contains unmapped logic. (RPT-7)
1
alias sc_onsyntax_checktrue
alias sc_off syntax_checkfalse
alias cc_oncontext_check true
alias cc_off context_check false
echo syntax_check_status
syntax_check_status
echo context_check_status
context_check_status
sc_off
Syntax checker off.
1
cc_on
Context checker on.
1
set_fsm_encoding_style binary
report_fsm
report_constraint
#fsm_auto_inferring true
#hdlin_reporting_level comprehensive
uniquify
#compile！
compile -exact_map -map_effort high
#generate netlist file (verilog)
write -hierarchy -output spi.db
write -format verilog -hierarchy -output /home/project/spi_syn/script/spi.sv
write_sdf -version 2.1/home/project/spi_syn/sdf/SPI_CORE.sdf
#write_sdcsdc_script_file.sdc
#save design before quit dc_shell(ddc)
write -format ddc-hierarchy -outputspi.ddc
set hdlin_report_inferred_modules verbose
verbose
#check_design
#/home/project/spi_syn/script/spi.v
dc_shell> quit

Memory usage for this session 26 Mbytes.
CPU usage for this session 1 seconds.

Thank you...

不想整的花里胡哨的，就直接绝对路径加文件名呗，最简单直接了