verilog/VCS 模块加密

You can use VCS to encrypt selected parts of your source files. In order to achieve this, complete the following steps:
1. Enclose the Verilog code that you want to encrypt between the
‘protect128 and the ‘endprotect128 compiler directives.
Enclose the VHDL code that you want to encrypt between the
--protect128 and --endprotect128 pragmas.
2. Analyze the files with the -protect128 option. For example:
% vlogan -protect128 foo.v
% vcs -protect128 foo.v

这个牛叉啊

大侠请问：
我有个.vp文件（`protected ... `endprotected）用NC-verilog可以编译和仿真，但在VCS中报错:
Error-[BE] Bad encryption
Started encryption outside a module or in another scope.
请问这是为啥么?