请教：set_multicycle_path

clock:pclk
DFF1:iap_fsm_reg_0
DFF2:iap_en_reg
DFF1/DFF2 Timing没问题。
DFF1/Q输出至Flash XE，DFF2/Q输出至Flash SE。
XE和SE有timing constraint，violation为hold，报告如下。
问题：如何设置multi cycle path，解决该问题。


Startpoint: A0_mcu_top/A2_apb_top/A0_apb_iap/iap_fsm_reg_0
(rising edge-triggered flip-flop clocked by pclk)
Endpoint: A0_mcu_top/A2_flash_16kx32
(rising edge-triggered data to data check clocked by pclk)
Path Group: pclk
Path Type: min
PointIncrPath
------------------------------------------------------------------------------
clock pclk (rise edge)0.000.00
clock network delay (propagated)3.433.43
A0_mcu_top/A2_apb_top/A0_apb_iap/iap_fsm_reg_0/CK (SDFFRHQX1)
0.003.43 r
A0_mcu_top/A2_apb_top/A0_apb_iap/iap_fsm_reg_0/Q (SDFFRHQX1)
0.25 &3.67 f
A0_mcu_top/A2_apb_top/A0_apb_iap/iap_xe (apb_iap)0.00 &3.67 f
A0_mcu_top/A2_apb_top/iap_xe (apb_top)0.00 &3.67 f
A0_mcu_top/A2_flash_mux/iap_xe (flash_mux)0.00 &3.67 f
A0_mcu_top/A2_flash_mux/U10/Y (AND3X2)0.16 &3.83 f
A0_mcu_top/A2_flash_mux/U6/Y (NAND4BX2)0.82 &4.65 f
A0_mcu_top/A2_flash_mux/flash_xe (flash_mux)0.00 &4.65 f
A0_mcu_top/A2_flash_16kx32/XE (SFD16KX32M32P4C5V_HE_ULL_C120830)
0.30 &4.95 f
data arrival time4.95
clock pclk (rise edge)0.000.00
clock network delay (propagated)3.433.43
A0_mcu_top/A2_apb_top/A0_apb_iap/iap_en_reg/CK (SDFFRHQX1)
0.003.43 r
A0_mcu_top/A2_apb_top/A0_apb_iap/iap_en_reg/Q (SDFFRHQX1)
0.35 &3.78 f
A0_mcu_top/A2_flash_mux/U183/Y (INVX1)0.16 &3.94 r
A0_mcu_top/A2_flash_mux/U28/Y (NAND3X1)0.09 &4.03 f
A0_mcu_top/A2_flash_mux/U23/Y (INVX1)0.44 &4.47 r
A0_mcu_top/A2_flash_mux/U41/Y (AOI22X1)0.15 &4.62 f
A0_mcu_top/A2_flash_mux/U40/Y (NAND2X4)0.57 &5.19 r
A0_mcu_top/A2_flash_16kx32/SE (SFD16KX32M32P4C5V_HE_ULL_C120830)
0.46 &5.64 r
data check hold time10.0015.64
data required time15.64
------------------------------------------------------------------------------
data required time15.64
data arrival time-4.95
------------------------------------------------------------------------------
slack (VIOLATED)-10.69

貌似 flash memory lib model 產生 data check hold time 10.00 ns, 請看一下 lib model 是否正確.

Flash IP的timing没有问题。
现在是2个DFF的输出，至Flash接口的问题。需要multi cycle完成两个DFF的输出至Flash的设置。Design没问题，就是约束怎么写的问题。