关于LVS运行的error
时间：10-02
整理：3721RD
点击：
在calibre下作LVS检查时，出现以下错误信息
Error: Duplicate connection to pin "R_FEATG[5]" in file "/home/xmj/SIFT/DRC/source/top.v.sp" at line 450956
Error: Duplicate connection to pin "R_FEATG[5]" in file "/home/xmj/SIFT/DRC/source/top.v.sp" at line 451405
Error: Duplicate connection to pin "R_FEATG[5]" in file "/home/xmj/SIFT/DRC/source/top.v.sp" at line 451925
然后查找sp网表，
Xcm_o1 central_memory_o1_dw_row10_dw_col10_dw_img11_dw_irw8 $PINS
+ we_f3=we_f3_o1 wen=n144 ren=n187 start_3dmax=start_3dmax_o1
+ start_domori=domori_proc_o1 ack_domori=ack_domori_o1 feat_ready=feat_ready_o1
+ ima_full_n=ima_full_n_o1 R_featg[5]=R_featg_o1[5] R_featg[4]=R_featg_o1[4]
+ R_featg[3]=R_featg_o1[3] R_featg[2]=R_featg_o1[2] R_featg[1]=R_featg_o1[1]
+ R_featg[0]=R_featg_o1[0] clk=clk_G1B6I1_1 rst=n354 clr=n400 we_f1=we_f1_o1
+ we_f2=we_f2_o1 r_featg[9]=r_featg_o1[9] r_featg[8]=r_featg_o1[8]
+ r_featg[7]=r_featg_o1[7] r_featg[6]=r_featg_o1[6] r_featg[5]=r_featg_o1[5]
Xcm_o2 central_memory_o2_dw_row9_dw_col9_dw_img11_dw_irw8 $PINS IN0=n1231
+ IN1=n1260 IN2=n518 IN3=n515 IN4=n1273 we_f2=we_f2_o2 we_f3=we_f3_o2 wen=n146
+ ren=ren_o2 start_3dmax=start_3dmax_o2 start_domori=domori_proc_o2
+ ack_domori=ack_domori_o2 feat_ready=N29 R_featg[5]=R_featg_o3[5]
+ R_featg[4]=R_featg_o3[4] R_featg[3]=R_featg_o3[3] R_featg[2]=R_featg_o3[2]
+ R_featg[1]=R_featg_o3[1] R_featg[0]=R_featg_o3[0] clk=clk_G1B7I30_1 rst=n354
+ clr=n402 we_f1=we_f1_o2 r_featg[8]=r_featg_o2R8R r_featg[7]=r_featg_o3[7]
+ r_featg[6]=r_featg_o3[6] r_featg[5]=r_featg_o3[5] r_featg[4]=r_featg_o3[4]
Xcm_o3 central_memory_o3_dw_row8_dw_col8_dw_img11_dw_irw8 $PINS
+ feat_ready=feat_ready_o3 IN0=n696 IN1=n694 IN2=n691 IN3=n688 we_f1=we_f1_o3
+ we_f2=we_f2_o3 we_f3=we_f3_o3 wen=n145 ren=ren_o3 start_3dmax=start_3dmax_o3
+ start_domori=domori_proc_o3 ack_domori=ack_domori_o3 R_featg[5]=R_featg_o3[5]
+ R_featg[4]=R_featg_o3[4] R_featg[3]=R_featg_o3[3] R_featg[2]=R_featg_o3[2]
+ R_featg[1]=R_featg_o3[1] R_featg[0]=R_featg_o3[0] clk=clk_G1B7I30_1 rst=n364
+ clr=n402 r_featg[7]=r_featg_o3[7] r_featg[6]=r_featg_o3[6]
+ r_featg[5]=r_featg_o3[5] r_featg[4]=r_featg_o3[4] r_featg[3]=r_featg_o3[3]
这是网表中对应的错误的部分，好像是重复连接了，请问为什么会发生这样的错误，怎样解决。
还有在lvs中哪里设置将以下两项开启
LAYOUT CASENO
SOURCE CASENO
Error: Duplicate connection to pin "R_FEATG[5]" in file "/home/xmj/SIFT/DRC/source/top.v.sp" at line 450956
Error: Duplicate connection to pin "R_FEATG[5]" in file "/home/xmj/SIFT/DRC/source/top.v.sp" at line 451405
Error: Duplicate connection to pin "R_FEATG[5]" in file "/home/xmj/SIFT/DRC/source/top.v.sp" at line 451925
然后查找sp网表，
Xcm_o1 central_memory_o1_dw_row10_dw_col10_dw_img11_dw_irw8 $PINS
+ we_f3=we_f3_o1 wen=n144 ren=n187 start_3dmax=start_3dmax_o1
+ start_domori=domori_proc_o1 ack_domori=ack_domori_o1 feat_ready=feat_ready_o1
+ ima_full_n=ima_full_n_o1 R_featg[5]=R_featg_o1[5] R_featg[4]=R_featg_o1[4]
+ R_featg[3]=R_featg_o1[3] R_featg[2]=R_featg_o1[2] R_featg[1]=R_featg_o1[1]
+ R_featg[0]=R_featg_o1[0] clk=clk_G1B6I1_1 rst=n354 clr=n400 we_f1=we_f1_o1
+ we_f2=we_f2_o1 r_featg[9]=r_featg_o1[9] r_featg[8]=r_featg_o1[8]
+ r_featg[7]=r_featg_o1[7] r_featg[6]=r_featg_o1[6] r_featg[5]=r_featg_o1[5]
Xcm_o2 central_memory_o2_dw_row9_dw_col9_dw_img11_dw_irw8 $PINS IN0=n1231
+ IN1=n1260 IN2=n518 IN3=n515 IN4=n1273 we_f2=we_f2_o2 we_f3=we_f3_o2 wen=n146
+ ren=ren_o2 start_3dmax=start_3dmax_o2 start_domori=domori_proc_o2
+ ack_domori=ack_domori_o2 feat_ready=N29 R_featg[5]=R_featg_o3[5]
+ R_featg[4]=R_featg_o3[4] R_featg[3]=R_featg_o3[3] R_featg[2]=R_featg_o3[2]
+ R_featg[1]=R_featg_o3[1] R_featg[0]=R_featg_o3[0] clk=clk_G1B7I30_1 rst=n354
+ clr=n402 we_f1=we_f1_o2 r_featg[8]=r_featg_o2R8R r_featg[7]=r_featg_o3[7]
+ r_featg[6]=r_featg_o3[6] r_featg[5]=r_featg_o3[5] r_featg[4]=r_featg_o3[4]
Xcm_o3 central_memory_o3_dw_row8_dw_col8_dw_img11_dw_irw8 $PINS
+ feat_ready=feat_ready_o3 IN0=n696 IN1=n694 IN2=n691 IN3=n688 we_f1=we_f1_o3
+ we_f2=we_f2_o3 we_f3=we_f3_o3 wen=n145 ren=ren_o3 start_3dmax=start_3dmax_o3
+ start_domori=domori_proc_o3 ack_domori=ack_domori_o3 R_featg[5]=R_featg_o3[5]
+ R_featg[4]=R_featg_o3[4] R_featg[3]=R_featg_o3[3] R_featg[2]=R_featg_o3[2]
+ R_featg[1]=R_featg_o3[1] R_featg[0]=R_featg_o3[0] clk=clk_G1B7I30_1 rst=n364
+ clr=n402 r_featg[7]=r_featg_o3[7] r_featg[6]=r_featg_o3[6]
+ r_featg[5]=r_featg_o3[5] r_featg[4]=r_featg_o3[4] r_featg[3]=r_featg_o3[3]
这是网表中对应的错误的部分，好像是重复连接了，请问为什么会发生这样的错误，怎样解决。
还有在lvs中哪里设置将以下两项开启
LAYOUT CASENO
SOURCE CASENO
错好像是大小写引起的
在lvs rule 任何地方可以加入
LAYOUT CASEYES
SOURCE CASEYES
谢谢，问题就是与这个有关，已经解决了，在lvsrule文件里面 添加上
LAYOUT CASE YES
SOURCE CASE YES
LVS COMPARE CASE YES
就可以了
谢谢，问题解决了，在lvs rule里面加上
LAYOUT CASE YES
SOURCE CASE YES
LVS COMPARE CASE YES
就可以了