Insertion of Tie Cell into the design,why after Placing？

Can you suggest the advantages of inserting the tie cells into the design after placing the instances, rather than inserting them into the design during logic synthesis?

为什么通常在Placing之后插入Filler而不是在逻辑综合时加入Filler?是有什么特别的考虑吗?

Tie high low cell需要考慮LOADING CAPACITANCE去處理, synthesis tool這個值是用估的沒辦法反映實際
所以都在APR PLACEMENT INSERT

Tie high low cell只是接到电源或者地电位，Tie high low cell的Loading对时序的影响大吗?还是其它方面的考虑?