DC出了一溜相同的警告，不太明白

Verilog writer has added 1 nets to module halfband3_DW02_mult_17 using SYNOPSYS_UNCONNECTED_ as prefix.Please use the change_names command to make th e correct changes before invoking the verilog writer.(VO-11)
就是上面这句话，其他警告就是把17这个数字换成了别的数字，还望论坛里的高手赐教我需要怎么做啊

Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
Warning: Verilog writer has added 1 nets to module halfband_DW02_mult_3 using SY NOPSYS_UNCONNECTED_ as prefix.Please use the change_names command to make the correct changes before invoking the verilog writer.(VO-11)
Warning: Verilog writer has added 1 nets to module halfband_DW02_mult_1 using SY NOPSYS_UNCONNECTED_ as prefix.Please use the change_names command to make the correct changes before invoking the verilog writer.(VO-11)
Warning: Verilog writer has added 27 nets to module halfband using SYNOPSYS_UNCO NNECTED_ as prefix.Please use the change_names command to make the correct cha nges before invoking the verilog writer.(VO-11)

初学者，还不太明白

暂时忽略

然后我在做ICC时就出现了很多类似下面的错误，还请赐教是怎么回事啊?
Error: Port 'halfband_out_f[2]' cannot inherit its location from the pin 'hb3/out_r_reg[18]/Q', because the cell 'hb3/out_r_reg[18]' is neither a pad-cell nor a macro-cell. Please check the library. (PSYN-117)

没看出来它们之间有什么联系

那后来这个错误是什么原因造成的?我们的指导老师根本就不会这个，全是我们自己在摸索

把完整的command和mesage贴出来