PR分析的Timing Violation。

PR时，CTS已经Insertion完毕，scan_mode set为0，报Function Clock到SDFF的SI端的Timing Violation。
SI端的violation应该scan_clock timing check时，需要check的。
下面是全warning。
Path 1: VIOLATED Hold Check with Pin A0_mcu_top/A2_apb_top/A0_modem_top/u_
encode/u_vtb/VTBcomparePath/candidate_d1_reg_36/CK
Endpoint:A0_mcu_top/A2_apb_top/A0_modem_top/u_encode/u_vtb/VTBcomparePath/
candidate_d1_reg_36/SI (^) checked withleading edge of 'MCU_CLK'
Beginpoint: A0_mcu_top/A2_apb_top/A0_modem_top/u_encode/u_vtb/VTBcomparePath/
candidate_d1_reg_37/Q(^) triggered byleading edge of 'MCU_CLK'
Path Groups:{reg2reg}
Other End Arrival Time2.209
+ Hold-0.140
+ Phase Shift0.000
+ Uncertainty0.500
= Required Time2.569
Arrival Time2.477
Slack Time-0.091
Clock Rise Edge0.000
= Beginpoint Arrival Time0.000
Timing Path:
+-------------------------------------------------------------------------------------------------------------------+
|Instance|Arc|Cell|Slew | Delay | Arrival | Required |
||||||Time|Time|
|----------------------------------------------------+-------------+-----------+-------+-------+---------+----------|
| A1_filter_fosc/INV_U0| Y ^|| 0.000 ||0.000 |0.091 |
| A0_mcu_top/A0_system_clock/U59| A ^ -> Y v| INVX2| 0.125 | 0.080 |0.080 |0.172 |
| A0_mcu_top/A0_system_clock/n59__L1_I0| A v -> Y ^| INVXL| 0.062 | 0.065 |0.145 |0.236 |
| A0_mcu_top/A0_system_clock/n59__L2_I0| A ^ -> Y v| INVXL| 0.061 | 0.053 |0.198 |0.290 |
| A0_mcu_top/A0_system_clock/U56| A0 v -> Y ^ | OAI32X2| 0.117 | 0.142 |0.340 |0.431 |
| A0_mcu_top/A0_system_clock/A0_clk_gen/U15| A ^ -> Y v| INVX3| 0.092 | 0.077 |0.417 |0.508 |
| A0_mcu_top/A0_system_clock/A0_clk_gen/U5| B1 v -> Y ^ | OAI22X4| 0.164 | 0.154 |0.571 |0.662 |
| A0_mcu_top/A0_system_clock/A0_pmu/u_fclk/U4| B ^ -> Y ^| AND2X4| 0.152 | 0.155 |0.726 |0.818 |
| A0_mcu_top/A0_system_clock/u_PCLK| A ^ -> Y ^| MX2X4| 0.111 | 0.159 |0.885 |0.976 |
| A0_mcu_top/A2_apb_top/A0_apb_clken/U176| B ^ -> Y v| NAND2BX4| 0.035 | 0.034 |0.919 |1.010 |
| A0_mcu_top/A2_apb_top/A0_apb_clken/U175| A v -> Y v| BUFX4| 0.092 | 0.126 |1.045 |1.136 |
| A0_mcu_top/A2_apb_top/A0_apb_clken/n21__L1_I3| A v -> Y v| CLKBUFX8| 0.154 | 0.170 |1.215 |1.307 |
| A0_mcu_top/A2_apb_top/A0_apb_clken/n21__L2_I4| A v -> Y ^| CLKINVX20 | 0.026 | 0.183 |1.398 |1.489 |
| A0_mcu_top/A2_apb_top/A0_apb_clken/n21__L3_I8| A ^ -> Y v| CLKINVX3| 0.131 | 0.088 |1.486 |1.578 |
| A0_mcu_top/A2_apb_top/A0_apb_clken/U11| A0 v -> Y ^ | OAI21X4| 0.116 | 0.152 |1.639 |1.730 |
| A0_mcu_top/A2_apb_top/modem_clk__L1_I1| A ^ -> Y v| CLKINVX20 | 0.116 | 0.187 |1.826 |1.917 |
| A0_mcu_top/A2_apb_top/modem_clk__L2_I11| A v -> Y ^| CLKINVX20 | 0.081 | 0.219 |2.045 |2.136 |
| A0_mcu_top/A2_apb_top/modem_clk__L3_I62| A ^ -> Y ^| BUFX16| 0.119 | 0.158 |2.203 |2.294 |
| A0_mcu_top/A2_apb_top/A0_modem_top/u_encode/u_vtb/ | CK ^ -> Q ^ | SEDFFX1| 0.145 | 0.274 |2.477 |2.568 |
| VTBcomparePath/candidate_d1_reg_37|||||||
| A0_mcu_top/A2_apb_top/A0_modem_top/u_encode/u_vtb/ | SI ^| SEDFFX1| 0.145 | 0.000 |2.477 |2.569 |
| VTBcomparePath/candidate_d1_reg_36|||||||
+-------------------------------------------------------------------------------------------------------------------+

检查A0_mcu_top/A2_apb_top/A0_modem_top/u_encode/u_vtb/VTBcomparePath/candidate_d1_reg_36/SE是否为0