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PR时required time 为负的问题

时间:10-02 整理:3721RD 点击:
部分报告如下:其中 Instance:HNCLK_DUT 为晶振
Clock Rise Edge0.000
= Beginpoint Arrival Time0.000
Other End Path:
+----------------------------------------------------------------------------------------------------------------+
|Instance|Arc|Cell|Slew | Delay | Arrival | Required |
||||||Time|Time|
|-------------------------------------------------+----------------+--------+-------+-------+---------+----------|
| HNCLK_DUT| OSCO ^|| 0.000 ||0.000 |-72.278 |
| CLK__L1_I2| H01 ^ -> N01 v | F148| 0.244 | 0.143 |0.143 |-72.135 |
| CLK__L2_I2| H01 v -> N01 ^ | F148| 0.313 | 0.163 |0.307 |-71.972 |
| CLK__L3_I2| H01 ^ -> N01 v | F148| 0.361 | 0.234 |0.541 |-71.737 |
| CLK__L4_I3| H01 v -> N01 ^ | F148| 0.314 | 0.180 |0.721 |-71.558 |
| CLK__L5_I4| H01 ^ -> N01 v | F148| 0.361 | 0.237 |0.958 |-71.321 |
| CLK__L6_I9| H01 v -> N01 ^ | F148| 0.473 | 0.247 |1.205 |-71.074 |
| AS1232_TOP_CORE_DUT/POWER_SAVE_DUT_COUNT_reg_7_ | H02 ^| L613NQ | 0.473 | 0.000 |1.205 |-71.073 |
+----------------------------------------------------------------------------------------------------------------+

自己顶一个
不能沉啊

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