power on sequence问题请教
时间：10-02
整理：3721RD
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hi everybody！
I was puzzled by power-on-sequence problem now.
I used to do a project using smic 130nm logic technology, using its standard io lib.
SMIC demand io power first, core power second sequence.
The reason behind this rule is ESD Diode between io power ring and core power ring in IO Cell circuit.
But, When I turn to TSMC tech, I find different rule, TSMC consider power on sequence only in IO Crowbar current, do not care ESD diode at all！
Why?
Who has TSMC power on sequence experience, can you share some idea on it?
Thanks！
I was puzzled by power-on-sequence problem now.
I used to do a project using smic 130nm logic technology, using its standard io lib.
SMIC demand io power first, core power second sequence.
The reason behind this rule is ESD Diode between io power ring and core power ring in IO Cell circuit.
But, When I turn to TSMC tech, I find different rule, TSMC consider power on sequence only in IO Crowbar current, do not care ESD diode at all！
Why?
Who has TSMC power on sequence experience, can you share some idea on it?
Thanks！
印象中smic控制上电顺序的是FP信号。
tsmc控制上电顺序的是POC信号。
上电时保证IO先上电，然后是core，否则会漏电。
两家其实原理上差不多！
我印象中也是这样的
注意FP有两根 FP FPB 全芯片均需要连起来，要不然漏电。
对，防治leakage的 ，
即使core先上电， 因为有POC,FP信号，也不会对芯片造成损失，
一般上电 要求先高压，再低压，关电是随便的，