Warning: A non-unate path in clock network(TIM-052)
时间：10-02
整理：3721RD
点击：
if clk source is generate clock + combination logic
for instance
always@(clkc, reset) ....
1. clkc= (reg0_bit0 ^ clkb) ->reg_bot0 xor clkb
2. clkb = clka/2 (generated form clka)
3. source clk=clka
it sould be always ( clkb ,...)
then dc can recongnize clkb is generate from clka
but
add reg0_bit0 just want to controlDFF clkc = posedge clkbor negedge clkb
Q :
howto add dc constrain to inform DC about the design we want to do?
for instance
always@(clkc, reset) ....
1. clkc= (reg0_bit0 ^ clkb) ->reg_bot0 xor clkb
2. clkb = clka/2 (generated form clka)
3. source clk=clka
it sould be always ( clkb ,...)
then dc can recongnize clkb is generate from clka
but
add reg0_bit0 just want to controlDFF clkc = posedge clkbor negedge clkb
Q :
howto add dc constrain to inform DC about the design we want to do?
Positive unate means the output rising due to the input rising,the output falling due to the input falling. Negative unate means the output rising due to the input falling,the output falling due to the input rising.Non unate means the output rising due to the input rising or falling, the output falling also due to the input rising or falling.