求助各位大神 本人刚学版图

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##C A L I B R ES Y S T E M##
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##L V SR E P O R T##
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REPORT FILE NAME:123.lvs.report
LAYOUT NAME:/home/xnj/csmcfile/m3524/libs/m3524/inv/lvs/123.sp ('123')
SOURCE NAME:/home/xnj/csmcfile/m3524/libs/m3524/inv/lvs/123.src.net ('123')
RULE FILE:/home/xnj/csmcfile/m3524/libs/m3524/inv/lvs/_cal35head.lvs_
CREATION TIME:Thu Oct 12 21:17:34 2017
CURRENT DIRECTORY:/home/xnj/csmcfile/m3524/libs/m3524/inv/lvs
USER NAME:xnj
CALIBRE VERSION:v2011.2_34.26Wed Jul 6 05:20:56 PDT 2011

OVERALL COMPARISON RESULTS

##########################
# ###
##NOT COMPARED#
# ###
##########################

Error:Different numbers of ports.
Error:Power or ground net missing.

**************************************************************************************************************
CELLSUMMARY
**************************************************************************************************************
ResultLayoutSource
------------------------------------
NOT COMPARED123123

**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************

o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME"VCC" "VDD" "vdd！"
LVS GROUND NAME"VSS" "GND" "GROUND" "gnd！"
LVS CELL SUPPLYNO
LVS RECOGNIZE GATESALL
LVS IGNORE PORTSNO
LVS CHECK PORT NAMESYES
LVS IGNORE TRIVIAL NAMED PORTSNO
LVS BUILTIN DEVICE PIN SWAPYES
LVS ALL CAPACITOR PINS SWAPPABLEYES
LVS DISCARD PINS BY DEVICENO
LVS SOFT SUBSTRATE PINSNO
LVS INJECT LOGICYES
LVS EXPAND UNBALANCED CELLSYES
LVS FLATTEN INSIDE CELLNO
LVS EXPAND SEED PROMOTIONSNO
LVS PRESERVE PARAMETERIZED CELLSNO
LVS GLOBALS ARE PORTSYES
LVS REVERSE WLNO
LVS SPICE PREFER PINSNO
LVS SPICE SLASH IS SPACEYES
LVS SPICE ALLOW FLOATING PINSYES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGSNO
LVS SPICE CONDITIONAL LDDNO
LVS SPICE CULL PRIMITIVE SUBCIRCUITSNO
LVS SPICE IMPLIED MOS AREANO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALSNO
LVS SPICE REDEFINE PARAMNO
LVS SPICE REPLICATE DEVICESNO
LVS SPICE SCALE X PARAMETERSNO
LVS SPICE STRICT WLNO
// LVS SPICE OPTION
LVS STRICT SUBTYPESNO
LVS EXACT SUBTYPESNO
LAYOUT CASENO
SOURCE CASENO
LVS COMPARE CASENO
LVS DOWNCASE DEVICENO
LVS REPORT MAXIMUM50
LVS PROPERTY RESOLUTION MAXIMUM32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITSYES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOSNO
LVS REDUCE PARALLEL MOSYES
LVS REDUCE SEMI SERIES MOSNO
LVS REDUCE SPLIT GATESYES
LVS REDUCE PARALLEL BIPOLARYES
LVS REDUCE SERIES CAPACITORSYES
LVS REDUCE PARALLEL CAPACITORSYES
LVS REDUCE SERIES RESISTORSYES
LVS REDUCE PARALLEL RESISTORSYES
LVS REDUCE PARALLEL DIODESYES
LVS REDUCTION PRIORITYPARALLEL
LVS SHORT EQUIVALENT NODESNO
// Trace Property
TRACE PROPERTYmn(n)l l 0
TRACE PROPERTYmn(n)w w 0
TRACE PROPERTYmn(nf)l l 0
TRACE PROPERTYmn(nf)w w 0
TRACE PROPERTYmn(nd)l l 0
TRACE PROPERTYmn(nd)w w 0
TRACE PROPERTYmn(ng)l l 0
TRACE PROPERTYmn(ng)w w 0
TRACE PROPERTYmp(p)l l 0
TRACE PROPERTYmp(p)w w 0
TRACE PROPERTYmp(pd)l l 0
TRACE PROPERTYmp(pd)w w 0
TRACE PROPERTYq(pn)a a 0
TRACE PROPERTYq(p2)a a 0
TRACE PROPERTYq(p3)a a 0
TRACE PROPERTYd(dn)a a 0
TRACE PROPERTYd(dm)a a 0
TRACE PROPERTYd(dp)a a 0
TRACE PROPERTYd(dc)a a 0
TRACE PROPERTYd(dk)a a 0
TRACE PROPERTYd(da)a a 0
TRACE PROPERTYd(db)a a 0
TRACE PROPERTYc(c1)c c 0
TRACE PROPERTYr(rt)r r 0
TRACE PROPERTYr(rs)r r 0
TRACE PROPERTYc(cm)c c 0
TRACE PROPERTYr(rw)r r 0
TRACE PROPERTYr(an)r r 0
TRACE PROPERTYr(ap)r r 0
TRACE PROPERTYr(po)r r 0
TRACE PROPERTYr(pl)r r 0
TRACE PROPERTYr(ph)r r 0

CELL COMPARISON RESULTS ( TOP LEVEL )

##########################
# ###
##NOT COMPARED#
# ###
##########################

Error:Different numbers of ports (see below).
Error:Power net missing in layout. Ground net missing in layout.
LAYOUT CELL NAME:123
SOURCE CELL NAME:123
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Ports:05*
Nets:46*
Instances:22MN (4 pins)
22MP (4 pins)
------------
Total Inst:44

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Ports:05*
Nets:35*
Instances:10*MP (4 pins)
01*_nand2v (5 pins)
10*_smn2v (4 pins)
------------
Total Inst:21

* = Number of objects in layout different from number in source.

**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************

o Statistics:
2 layout mos transistors were reduced to 1.
1 mos transistor was deleted by parallel reduction.

**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time:0 sec
Total Elapsed Time:0 sec

版图上面端口没标吧

版图上面端口没标

版图没有打PORT，或者PORT层次不对

能再指教一下么，刚开始学不太懂啊，拜托了

port用的是哪一层打的?

用metal相对应的text层

先让电源识别到就不会"NOT COMPARE"了，看你的图是打了text没有识别到，应该还是层次有问题，可以看看你用的制程是用哪层layer打label

Layout打PORT 的layer層不對，可以參考disclaimer Layer_Definition

你好！我也是版图新手！也出现小编一样的问题，用用metal的tt层标端口后，出现了如照片的问题，该怎么解决?望不吝赐教

PORT层次不对

看报错应该是PORT的层次不对，每个工艺可能会有差别，并不是每个工艺都用text层，去看看你的DR文档，里面应该有说用哪一层

刚好我也在用上华工艺，文件报了你点版图里面识别到port， 电源没认出来。 打label 用A1TEXT（metal1的）/A2TEXT（metal2）