Global Foundries急招前端/后端/memory/analog designer以及lay
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公司业务扩张，急需以下人才：
JD比较宽泛，有兴趣的同学加QQ 121958419详聊 或者直接发简历至QQ邮箱，谢谢！
PD Methodology Engineer (Job Number: 17003752)
Backend Design Engineer(Job Number: 16002520)
Memory Design Engineer(Job Number: 16002521)
IP Applications Engineer(Job Number: 16002929)
Logic VerificationEngineer (Job Number: 16002932)
Analog Design Engineer(Job Number: 17000001)
HSS/DDR ApplicationEngineer (Job Number: 17000002)
Layout Design Engineer(Job Number: 17000003)
Logic Design Engineer (Job Number: 17000004)
Package Design Engineer(Job Number: 17000042)
Power Supply Noise Engineer (Job Number: 17000046)
Customer Quality Engineer (Job Number: 17000049)
Manager Ecosystem Partnership and University Relations - Shanghai (Job Number: 17003687)
Director Marketing Programs (Job Number: 16001893)
Sr Mgr/Dep Dir ProdManagement (Job Number: 17000865)
PMTS Packaging Engneer (Job Number: 17002991)
Sr Staff Account Manager (Job Number: 17001609)
SMTS Design Enablement (Job Number: 17000490)
SMTS Design Enablement (Job Number: 17000121)
MTS Design Enablement (Analog Design & Layout) (Job Number: 17002620, 17002615, 17002604)
具体岗位要求：
PD Methodology Engineer (Job Number: 17003752)
GLOBALFOUNRIES ASIC methodology team is seeking experienced methodology engineers. You will be involved in the commencement, development and enhancement PD implementation flow and design methodology of leading edge technologies such as 14nm, 7nm, 22FD-SOI, etc. You'll work with industry-leading methodology and technology enablement specialists and be responsible for development activities ranging from flow architect, methodology developing, early design enablement, and design system validation. This opportunity offers an exciting career path in leading edge high-end ASIC technologies and the digital design chip implementation.
Description
Physical design methodology development and enhancement for leading edge technologies of ASIC, including floorplanning, placement, design opt, clocking, routing, power opt, timing closure, physical verification, etc.
Enable design team for design flow flush, trouble-shooting, QoR improvement, and chip completeness.
Support design team for implementation of requests for special design flow/methodology customization of productivity enhancement.
Develop on-demand minor flow for design optimization and PD/timing closure.
System-level design flow qualification with world-wide methodology team.
Qualifications
6-10 years of experience in the following areas:
Physical/timing experience in ASIC design, development experience of high volume and high reliability ASIC chips in customer products.
Strong background in digital ASIC design preferably in networking and switching chips.
Strong expertise of ASIC physical implementation flow: floorplanning, power planning, top-down/bottom-up flow, placement/opt/routing, power consumption optimization, and design closure.
Strong expertise of scripting and design automation of design jobs.
Excellent written and verbal communication skills and solid teamwork and leadership skills.
Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation.
Working knowledge of TCL/TK, Perl/Python, Shell script, C/C++ language.
Backend Design Engineer (Job Number: 16002520)
Description
The backend design engineer will be participating in the development of:
Design for Test
Physical implementation and optimization
Package and electrical design
Electronic Design Automation (EDA) & methodology development and deployment
Chip hardware validation.
Qualifications
CS/EE or background in areas related to digital or analog chip design
Min 1 year+ work experience in chip design
Research and development experience in one or more of the following areas:
○ ASIC back-end design methodology: Knowledge of floor planning, physical design, timing, DFT, signal/power integrity, packaging, synthesis, and other back-end activities
○ EDA algorithm, tool, and methodology development.
○ Experience/knowledge in analog and mixed-signal IP design, test and evaluation with Bulk CMOS, BiCMOS, SiGe, or SOI technologies
○ Proficiency in Verilog/VHDL, and familiarity with programming and scripting languages
Experience in one or some of the application domains, will be a plus
○ High performance computing (servers) system, processor, chipset and ASICs
○ Communication, networking and wireless applications
○ DSP, RISC Processor architecture, Digital media, audio/video graphic and gaming processing
○ Consumer electronics applications
○ High Speed Interface/Serdes applications
○ Good software background and strong C/C++ skill
○ Other emerging technology and industry areas
Good English skills, communication skills, and willingness to work with a global team. Skill in other languages will be a plus.
Good learning competency and ability to work in diverse areas in a flexible environment
Memory Design Engineer(Job Number: 16002521)
Description
GLOBALFOUNDRIES Memory Design Engineer is working on cutting-edge embedded Memory IP development for GLOBALFOUNDRIES worldwide clients, including SRAM, RF, TCAM, ROM, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies including 14nm and beyond, you will be participating in:
Design full custom circuits in the embedded memory arrays
Simulate, verify and analyze memory functionality, performance and statistical margin
Perform functional verification, characterization and model-to-hardware correlation
Evaluate and optimize memory architecture and methodology in cutting-edge techno
Qualifications
ME/EE or background in related areas.
Experience in one or more of the following embedded or standalone memory products/circuits: SRAM, DRAM, Flash, Register File, TCAM, ROM, etc.
Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE, etc.).
Good understanding of advanced semiconductor technology process and device physics.
Experience with statistical circuit analysis and simulation is a plus.
Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.
Good learning competency and ability to work in diverse areas in a flexible environment
IP Applications Engineer (Job Number: 16002929)
Description
The IP Applications Engineer is the first line interface to the customer for all aspects related to INVECAS IP products, including day to day customer support, helping customers integrate IP into their designs, training, presentation, problem solving, getting feedback and more. The IPAE brings customer feedback internally to improve INVECAS IP products and customer service.
Responsibilities:
Interface with customers to support integration of IP into customer designs
Understand and communicate customer IP requirements to design and marketing teams
Answer customer questions on IP products or re-assign to internal IP support groups
Receive customer service requests and questions, screen, categorize, prioritize and assign to internal support groups
Leverage the IP Management System to track all customer IP deliveries, updates, service requests, open and closed cases
Interface with customers to gather regular feedback on INVECAS IP products, score card, service quality and customer satisfaction
Help in evaluation, benchmarking, design in and bring up of IP products
Gather from customers and report on market intelligence, new product requests, competitive moves, IP PPA competitiveness, new industry standards, etc. to drive new IP product development or improvement
Attend relevant industry standard committee meetings to learn about upcoming changes or new standards to help INVECAS develop new competitive IP products ahead of competition and to be the spokespersons of INVECAS therein
Develop relevant technical seminar material, webinars, videos, demo systems showcasing INVECAS IP at trade shows, events, etc.
Qualifications
Bachelor’s degree or equivalent in Electronics Engineering, Computer Science, or closely related field. MSEE is preferred.
At least 5 years of relevant experience in Semiconductor IP/Library Design (standard cells, memories, I/O’s, Analog Blocks, PHY/Serdes), preferably as a former design or applications engineer.
Experience with qualification and integration of various IPs into ASIC/SoC.
Experience with either Front or Back-end (Including HSPICE) tools from Synopsys and Cadence.
A deep understanding of IP design, ASIC Design Flow and integration related issues.
Excellent verbal and written communication skills. Proven customer facing skills.
Experience with creating various applications materials
Logic Verification Engineer (Job Number: 16002932)
Description
GLOBALFOUNDRIES Logic Verification Engineer is working on cutting-edge Digital and Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the front-end logic verification or mixed signal verification.
Requirements:
1. ME/EE/CS or background in related areas.
2. Research and/or development experience in one or more of the following areas:
Logic verification on the basis of the target system specification
Mixed-signal model verification on advanced technologies
Proficiency in programming and/or scripting languages is a plus
Knowledge on Protocols, High Speed Serdes or DDR is a plus
3. Experience in one or more of the following application domains, is a plus
High performance computing system, processor, chipset and ASICs
High end communication, networking, mobile and data center applications
Digital signal processing, sensor and Internet of Things
Other emerging IT technology and industry areas
Analog Design Engineer (Job Number: 17000001)
Description
GLOBALFOUNDRIES Analog Design Engineer is working on cutting-edge Analog and Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients, including High Speed Serial Links, PLL, ADC/DAC, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm, 7nm and beyond, you will be participating in the definition, design, layout, and characterization of the analog and mixed-signal circuits.
Qualifications
1. ME/EE or background in related areas.
2. Solid industry analog design or verification experience and hands-on practice.
3. Able to design circuits that operate effectively within the process window, and supervise layout floorplan and design.
4. Demonstrate good knowledge and experience in advanced analog and mixed-signal circuit design, experience in one or more of the following circuits, is a plus:
Driver / Receiver
Serializer / Deserializer
Phase Interpolator
VCO, Charge Pump, Clock Divider, PFD
Bias, Bandgap, Voltage Regulators
ADC, DAC
5. Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE, etc.).
6. Good understanding of advanced semiconductor technology process and device physics.
7. Experience with system level modeling and simulation by MATLAB, Verilog-A or C/C++ is a plus.
8. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.
9. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
HSS/DDR Application Engineer (Job Number: 17000002)
Description
GLOBALFOUNDRIES HSS/DDR Application Engineer is working on cutting-edge High Speed SerDes (HSS) and DDR IP engagement and support for GLOBALFOUNDRIES worldwide clients. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in:
Provide direct technical customer support and assistance to enable customers to successfully use HSS/DDR in their chip
Engage in hardware bring up and quality test support, including issue debug, electrical parameter measurement and HSS/DDR interface/register analysis
Enable physical integration of HSS/DDR in backend design process
Provide customer feedback on requirements for HSS/DDR to internal development team
Provide customer reference of board level circuit design on HSS/DDR interface
Write application notes and review specifications for HSS/DDR
Qualifications
1. ME/EE/CS or background in related areas.
2. At least 3 years industry application engineering experience.
3. Experience and knowledge in one or more of the following areas:
HSS or DDR customer application support
Hardware bring up and quality test support
High speed link or memory interface protocols including JEDEC, PCIE, IEEE and OIF
High speed link or memory interface design and verification experience is a plus
High speed board design and validation experience is a plus
4. Good understanding of chip backend design flow and methodology.
5. Able to conduct flexible hour technical meetings, seminars and trainings to customers.
6. Business travel within greater China region is required.
7. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.
8. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
Layout Design Engineer (Job Number: 17000003)
Description
GLOBALFOUNDRIES Layout Design Engineers at are responsible for circuit layouts development for our industry-leading IP offerings, including SerDes, memory, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor cutting-edge technologies ranging from 14nm and beyond, the layout design engineer is responsible of the floorplanning, physical design and verifications.
Qualifications
1. BS and above in Electrical or Related Areas.
2. Good understanding of advanced semiconductor technology process and device physics.
3. Full-custom circuit layout/verification and RC extraction experience. Experiences in one or more of the following area is preferable:
Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc.
High performance/capacity memory layout, e.g. SRAM, RF, RA, etc.
4. Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc).
5. Experiences in advanced technology node under 32nm/28nm/16nm/14nm and FINFET is preferable.
6. Experiences with EMIR analysis, ESD, antenna and related layout solutions is preferable.
7. Good English skills, communication skills, and willingness to work with a global team.
8. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
Logic Design Engineer (Job Number: 17000004)
Description
GLOBALFOUNDRIES Logic Design Engineer is working on cutting-edge Digital and Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the front-end logic design or mixed signal design.
Qualifications
1. ME/EE/CS or background in related areas.
2. Research and/or development experience in one or more of the following areas:
Logic design on the basis of the target system specification
Mixed-signal design on advanced technologies
Proficiency in programming and/or scripting languages is a plus
Knowledge on Protocols, High Speed Serdes or DDR is a plus
3. Experience in one or more of the following application domains, is a plus
High performance computing system, processor, chipset and ASICs
High end communication, networking, mobile and data center applications
Digital signal processing, sensor and Internet of Things
Other emerging IT technology and industry areas
4. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.
5. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
Package Design Engineer (Job Number: 17000042)
Description
GLOBALFOUNDRIES Package Design Engineer is responsible for large scale ASIC package definition, package model extraction, system-module SI/PI co-simulation and thermal/reliability solution. Support ASIC chip designs on IO planning based on GLOBALFOUNDRIES 32nm, 14nm and beyond technology. Design of high-speed package escape patterns and power delivery structures. Manage ASIC package laminate design from definition to manufacture. Explore advanced package solutions such as 2.5D, 3D package. Development of tools in support of image/package/PCB co-design.
Work scope includes but not limited to:
Package solution consulting and evaluation during project bid stage
Define package netlist based on chip-package co-design methodology
IO planning together with physical designer
Package ERC checking, package design file checking
Support customer on system-module SI/PI co-simulation
Package design sign-off
Develop package design methodology in China Design Center
Develop advanced 2.5D, 3D package design solution
The candidate would also have future extended responsibility participating in the design planning and sizing for the advanced ASIC/SoC chips, deployment and other application engineering support of the design methodology.
Qualifications
1. EE/ME/CS related background in system/chip design
2. Solid knowledge and extensive industry experience in one or more of the following areas:
○ High speed package/system design experience (High Speed Serdes, HBM, DDR, etc...)
○ Familiar with Industry SI/PI analysis process, system level modeling and finite element analysis tools (Ansys HSFF, Sigrity, SigXp, Spice, MATLAB, etc...)
○ Multiple layers PCB/Laminate (4+) layout experience (Experience with automation, such as cadence APD and related design tools, and SKILL language programming is a plus)
3. Good grasp of Perl/TCL scripts under Linux/Unix environment. C programming will be a plus.
4. Good communication skill in both English and Mandarin, and willingness to work with a global team. Skill in other languages is a plus.
5. Understanding of ASIC physical design process/tools, advanced semiconductor technology process and device physics is a plus
6. Strong teamwork sense, good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
7. Direct package engineer role with industry experience
JD比较宽泛，有兴趣的同学加QQ 121958419详聊 或者直接发简历至QQ邮箱，谢谢！
PD Methodology Engineer (Job Number: 17003752)
Backend Design Engineer(Job Number: 16002520)
Memory Design Engineer(Job Number: 16002521)
IP Applications Engineer(Job Number: 16002929)
Logic VerificationEngineer (Job Number: 16002932)
Analog Design Engineer(Job Number: 17000001)
HSS/DDR ApplicationEngineer (Job Number: 17000002)
Layout Design Engineer(Job Number: 17000003)
Logic Design Engineer (Job Number: 17000004)
Package Design Engineer(Job Number: 17000042)
Power Supply Noise Engineer (Job Number: 17000046)
Customer Quality Engineer (Job Number: 17000049)
Manager Ecosystem Partnership and University Relations - Shanghai (Job Number: 17003687)
Director Marketing Programs (Job Number: 16001893)
Sr Mgr/Dep Dir ProdManagement (Job Number: 17000865)
PMTS Packaging Engneer (Job Number: 17002991)
Sr Staff Account Manager (Job Number: 17001609)
SMTS Design Enablement (Job Number: 17000490)
SMTS Design Enablement (Job Number: 17000121)
MTS Design Enablement (Analog Design & Layout) (Job Number: 17002620, 17002615, 17002604)
具体岗位要求：
PD Methodology Engineer (Job Number: 17003752)
GLOBALFOUNRIES ASIC methodology team is seeking experienced methodology engineers. You will be involved in the commencement, development and enhancement PD implementation flow and design methodology of leading edge technologies such as 14nm, 7nm, 22FD-SOI, etc. You'll work with industry-leading methodology and technology enablement specialists and be responsible for development activities ranging from flow architect, methodology developing, early design enablement, and design system validation. This opportunity offers an exciting career path in leading edge high-end ASIC technologies and the digital design chip implementation.
Description
Physical design methodology development and enhancement for leading edge technologies of ASIC, including floorplanning, placement, design opt, clocking, routing, power opt, timing closure, physical verification, etc.
Enable design team for design flow flush, trouble-shooting, QoR improvement, and chip completeness.
Support design team for implementation of requests for special design flow/methodology customization of productivity enhancement.
Develop on-demand minor flow for design optimization and PD/timing closure.
System-level design flow qualification with world-wide methodology team.
Qualifications
6-10 years of experience in the following areas:
Physical/timing experience in ASIC design, development experience of high volume and high reliability ASIC chips in customer products.
Strong background in digital ASIC design preferably in networking and switching chips.
Strong expertise of ASIC physical implementation flow: floorplanning, power planning, top-down/bottom-up flow, placement/opt/routing, power consumption optimization, and design closure.
Strong expertise of scripting and design automation of design jobs.
Excellent written and verbal communication skills and solid teamwork and leadership skills.
Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation.
Working knowledge of TCL/TK, Perl/Python, Shell script, C/C++ language.
Backend Design Engineer (Job Number: 16002520)
Description
The backend design engineer will be participating in the development of:
Design for Test
Physical implementation and optimization
Package and electrical design
Electronic Design Automation (EDA) & methodology development and deployment
Chip hardware validation.
Qualifications
CS/EE or background in areas related to digital or analog chip design
Min 1 year+ work experience in chip design
Research and development experience in one or more of the following areas:
○ ASIC back-end design methodology: Knowledge of floor planning, physical design, timing, DFT, signal/power integrity, packaging, synthesis, and other back-end activities
○ EDA algorithm, tool, and methodology development.
○ Experience/knowledge in analog and mixed-signal IP design, test and evaluation with Bulk CMOS, BiCMOS, SiGe, or SOI technologies
○ Proficiency in Verilog/VHDL, and familiarity with programming and scripting languages
Experience in one or some of the application domains, will be a plus
○ High performance computing (servers) system, processor, chipset and ASICs
○ Communication, networking and wireless applications
○ DSP, RISC Processor architecture, Digital media, audio/video graphic and gaming processing
○ Consumer electronics applications
○ High Speed Interface/Serdes applications
○ Good software background and strong C/C++ skill
○ Other emerging technology and industry areas
Good English skills, communication skills, and willingness to work with a global team. Skill in other languages will be a plus.
Good learning competency and ability to work in diverse areas in a flexible environment
Memory Design Engineer(Job Number: 16002521)
Description
GLOBALFOUNDRIES Memory Design Engineer is working on cutting-edge embedded Memory IP development for GLOBALFOUNDRIES worldwide clients, including SRAM, RF, TCAM, ROM, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies including 14nm and beyond, you will be participating in:
Design full custom circuits in the embedded memory arrays
Simulate, verify and analyze memory functionality, performance and statistical margin
Perform functional verification, characterization and model-to-hardware correlation
Evaluate and optimize memory architecture and methodology in cutting-edge techno
Qualifications
ME/EE or background in related areas.
Experience in one or more of the following embedded or standalone memory products/circuits: SRAM, DRAM, Flash, Register File, TCAM, ROM, etc.
Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE, etc.).
Good understanding of advanced semiconductor technology process and device physics.
Experience with statistical circuit analysis and simulation is a plus.
Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.
Good learning competency and ability to work in diverse areas in a flexible environment
IP Applications Engineer (Job Number: 16002929)
Description
The IP Applications Engineer is the first line interface to the customer for all aspects related to INVECAS IP products, including day to day customer support, helping customers integrate IP into their designs, training, presentation, problem solving, getting feedback and more. The IPAE brings customer feedback internally to improve INVECAS IP products and customer service.
Responsibilities:
Interface with customers to support integration of IP into customer designs
Understand and communicate customer IP requirements to design and marketing teams
Answer customer questions on IP products or re-assign to internal IP support groups
Receive customer service requests and questions, screen, categorize, prioritize and assign to internal support groups
Leverage the IP Management System to track all customer IP deliveries, updates, service requests, open and closed cases
Interface with customers to gather regular feedback on INVECAS IP products, score card, service quality and customer satisfaction
Help in evaluation, benchmarking, design in and bring up of IP products
Gather from customers and report on market intelligence, new product requests, competitive moves, IP PPA competitiveness, new industry standards, etc. to drive new IP product development or improvement
Attend relevant industry standard committee meetings to learn about upcoming changes or new standards to help INVECAS develop new competitive IP products ahead of competition and to be the spokespersons of INVECAS therein
Develop relevant technical seminar material, webinars, videos, demo systems showcasing INVECAS IP at trade shows, events, etc.
Qualifications
Bachelor’s degree or equivalent in Electronics Engineering, Computer Science, or closely related field. MSEE is preferred.
At least 5 years of relevant experience in Semiconductor IP/Library Design (standard cells, memories, I/O’s, Analog Blocks, PHY/Serdes), preferably as a former design or applications engineer.
Experience with qualification and integration of various IPs into ASIC/SoC.
Experience with either Front or Back-end (Including HSPICE) tools from Synopsys and Cadence.
A deep understanding of IP design, ASIC Design Flow and integration related issues.
Excellent verbal and written communication skills. Proven customer facing skills.
Experience with creating various applications materials
Logic Verification Engineer (Job Number: 16002932)
Description
GLOBALFOUNDRIES Logic Verification Engineer is working on cutting-edge Digital and Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the front-end logic verification or mixed signal verification.
Requirements:
1. ME/EE/CS or background in related areas.
2. Research and/or development experience in one or more of the following areas:
Logic verification on the basis of the target system specification
Mixed-signal model verification on advanced technologies
Proficiency in programming and/or scripting languages is a plus
Knowledge on Protocols, High Speed Serdes or DDR is a plus
3. Experience in one or more of the following application domains, is a plus
High performance computing system, processor, chipset and ASICs
High end communication, networking, mobile and data center applications
Digital signal processing, sensor and Internet of Things
Other emerging IT technology and industry areas
Analog Design Engineer (Job Number: 17000001)
Description
GLOBALFOUNDRIES Analog Design Engineer is working on cutting-edge Analog and Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients, including High Speed Serial Links, PLL, ADC/DAC, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm, 7nm and beyond, you will be participating in the definition, design, layout, and characterization of the analog and mixed-signal circuits.
Qualifications
1. ME/EE or background in related areas.
2. Solid industry analog design or verification experience and hands-on practice.
3. Able to design circuits that operate effectively within the process window, and supervise layout floorplan and design.
4. Demonstrate good knowledge and experience in advanced analog and mixed-signal circuit design, experience in one or more of the following circuits, is a plus:
Driver / Receiver
Serializer / Deserializer
Phase Interpolator
VCO, Charge Pump, Clock Divider, PFD
Bias, Bandgap, Voltage Regulators
ADC, DAC
5. Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE, etc.).
6. Good understanding of advanced semiconductor technology process and device physics.
7. Experience with system level modeling and simulation by MATLAB, Verilog-A or C/C++ is a plus.
8. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.
9. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
HSS/DDR Application Engineer (Job Number: 17000002)
Description
GLOBALFOUNDRIES HSS/DDR Application Engineer is working on cutting-edge High Speed SerDes (HSS) and DDR IP engagement and support for GLOBALFOUNDRIES worldwide clients. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in:
Provide direct technical customer support and assistance to enable customers to successfully use HSS/DDR in their chip
Engage in hardware bring up and quality test support, including issue debug, electrical parameter measurement and HSS/DDR interface/register analysis
Enable physical integration of HSS/DDR in backend design process
Provide customer feedback on requirements for HSS/DDR to internal development team
Provide customer reference of board level circuit design on HSS/DDR interface
Write application notes and review specifications for HSS/DDR
Qualifications
1. ME/EE/CS or background in related areas.
2. At least 3 years industry application engineering experience.
3. Experience and knowledge in one or more of the following areas:
HSS or DDR customer application support
Hardware bring up and quality test support
High speed link or memory interface protocols including JEDEC, PCIE, IEEE and OIF
High speed link or memory interface design and verification experience is a plus
High speed board design and validation experience is a plus
4. Good understanding of chip backend design flow and methodology.
5. Able to conduct flexible hour technical meetings, seminars and trainings to customers.
6. Business travel within greater China region is required.
7. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.
8. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
Layout Design Engineer (Job Number: 17000003)
Description
GLOBALFOUNDRIES Layout Design Engineers at are responsible for circuit layouts development for our industry-leading IP offerings, including SerDes, memory, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor cutting-edge technologies ranging from 14nm and beyond, the layout design engineer is responsible of the floorplanning, physical design and verifications.
Qualifications
1. BS and above in Electrical or Related Areas.
2. Good understanding of advanced semiconductor technology process and device physics.
3. Full-custom circuit layout/verification and RC extraction experience. Experiences in one or more of the following area is preferable:
Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc.
High performance/capacity memory layout, e.g. SRAM, RF, RA, etc.
4. Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc).
5. Experiences in advanced technology node under 32nm/28nm/16nm/14nm and FINFET is preferable.
6. Experiences with EMIR analysis, ESD, antenna and related layout solutions is preferable.
7. Good English skills, communication skills, and willingness to work with a global team.
8. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
Logic Design Engineer (Job Number: 17000004)
Description
GLOBALFOUNDRIES Logic Design Engineer is working on cutting-edge Digital and Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the front-end logic design or mixed signal design.
Qualifications
1. ME/EE/CS or background in related areas.
2. Research and/or development experience in one or more of the following areas:
Logic design on the basis of the target system specification
Mixed-signal design on advanced technologies
Proficiency in programming and/or scripting languages is a plus
Knowledge on Protocols, High Speed Serdes or DDR is a plus
3. Experience in one or more of the following application domains, is a plus
High performance computing system, processor, chipset and ASICs
High end communication, networking, mobile and data center applications
Digital signal processing, sensor and Internet of Things
Other emerging IT technology and industry areas
4. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus.
5. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
Package Design Engineer (Job Number: 17000042)
Description
GLOBALFOUNDRIES Package Design Engineer is responsible for large scale ASIC package definition, package model extraction, system-module SI/PI co-simulation and thermal/reliability solution. Support ASIC chip designs on IO planning based on GLOBALFOUNDRIES 32nm, 14nm and beyond technology. Design of high-speed package escape patterns and power delivery structures. Manage ASIC package laminate design from definition to manufacture. Explore advanced package solutions such as 2.5D, 3D package. Development of tools in support of image/package/PCB co-design.
Work scope includes but not limited to:
Package solution consulting and evaluation during project bid stage
Define package netlist based on chip-package co-design methodology
IO planning together with physical designer
Package ERC checking, package design file checking
Support customer on system-module SI/PI co-simulation
Package design sign-off
Develop package design methodology in China Design Center
Develop advanced 2.5D, 3D package design solution
The candidate would also have future extended responsibility participating in the design planning and sizing for the advanced ASIC/SoC chips, deployment and other application engineering support of the design methodology.
Qualifications
1. EE/ME/CS related background in system/chip design
2. Solid knowledge and extensive industry experience in one or more of the following areas:
○ High speed package/system design experience (High Speed Serdes, HBM, DDR, etc...)
○ Familiar with Industry SI/PI analysis process, system level modeling and finite element analysis tools (Ansys HSFF, Sigrity, SigXp, Spice, MATLAB, etc...)
○ Multiple layers PCB/Laminate (4+) layout experience (Experience with automation, such as cadence APD and related design tools, and SKILL language programming is a plus)
3. Good grasp of Perl/TCL scripts under Linux/Unix environment. C programming will be a plus.
4. Good communication skill in both English and Mandarin, and willingness to work with a global team. Skill in other languages is a plus.
5. Understanding of ASIC physical design process/tools, advanced semiconductor technology process and device physics is a plus
6. Strong teamwork sense, good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
7. Direct package engineer role with industry experience