你想做SOC level的验证吗？
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华芯通是一家取得高通授权，开发基于ARM的大规模服务器芯片，现在上海地区高薪大量招聘soc level芯片验证工程师。
芯片验证一般包含IP level验证，SOC level验证，FPGA验证，以及emulation验证。那么，对于华芯通的SOC level验证，你能获得以下knowledge
1. 接触到最新的ARM多核架构，系统级的data path。
2. 理解和学到超大规模复杂的多核ARM的系统级boot流程。
3. 接触到常见的高速外设（DDR/MAC/SATA/USB）, 及其相关的工作原理，配置过程。
4. 接触到成百上千个复杂的clock和reset的片上网络，以及异步处理过程。
5. 有机会接触到如此庞大的服务器芯片，它的NOC （network of chip，片上网络）是如何实现上百个IP的互联的。
6. 接触到复杂的Low Power design
7. 有机会开发system UVC，各种checker/monitor， etc， 以及学习到复杂的SOC UVM环境。
所有这些对SOC level的验证提出很高的要求， 如果你想进一步提高个人综合实战能力，愿意加入华芯通SOC level验证大家庭，那就请发送简历到下面的邮箱， 我们定会给出你满意的薪资。这对于个人职业规划也是一个里程碑。
随时发送简历到qiang.wang@hxt-semitech.com
上海办公地点： 展想广场1号楼（距离2号线广兰路地铁站300米左右）
以下是职位的基本要求，是从HR那里拿到的公用模板，仅作为参考。
职位title： senior/staff engineer
Job Description: Responsibility:
Responsible for all aspects of verification on next generation integrated processors, including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:
- Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
- Develop System Verilog (UVM) random sequences and methods.
- Maintain and Interface with existing random generators, models and APIs
- Integration of random modules to various testbenches.
- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.
Requirement:
- Complex ASIC/SOC Design Verification, direct experience in SOC or Processor is preferred.
- Good knowledge of SystemVerilog and UVM is a plus.
- Good knowledge of Verilog/C/C++/System C/SystemVerilog.
- Verification insights into random techniques.
- Verification of large scale ASICs.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
- Background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
芯片验证一般包含IP level验证，SOC level验证，FPGA验证，以及emulation验证。那么，对于华芯通的SOC level验证，你能获得以下knowledge
1. 接触到最新的ARM多核架构，系统级的data path。
2. 理解和学到超大规模复杂的多核ARM的系统级boot流程。
3. 接触到常见的高速外设（DDR/MAC/SATA/USB）, 及其相关的工作原理，配置过程。
4. 接触到成百上千个复杂的clock和reset的片上网络，以及异步处理过程。
5. 有机会接触到如此庞大的服务器芯片，它的NOC （network of chip，片上网络）是如何实现上百个IP的互联的。
6. 接触到复杂的Low Power design
7. 有机会开发system UVC，各种checker/monitor， etc， 以及学习到复杂的SOC UVM环境。
所有这些对SOC level的验证提出很高的要求， 如果你想进一步提高个人综合实战能力，愿意加入华芯通SOC level验证大家庭，那就请发送简历到下面的邮箱， 我们定会给出你满意的薪资。这对于个人职业规划也是一个里程碑。
随时发送简历到qiang.wang@hxt-semitech.com
上海办公地点： 展想广场1号楼（距离2号线广兰路地铁站300米左右）
以下是职位的基本要求，是从HR那里拿到的公用模板，仅作为参考。
职位title： senior/staff engineer
Job Description: Responsibility:
Responsible for all aspects of verification on next generation integrated processors, including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:
- Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
- Develop System Verilog (UVM) random sequences and methods.
- Maintain and Interface with existing random generators, models and APIs
- Integration of random modules to various testbenches.
- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.
Requirement:
- Complex ASIC/SOC Design Verification, direct experience in SOC or Processor is preferred.
- Good knowledge of SystemVerilog and UVM is a plus.
- Good knowledge of Verilog/C/C++/System C/SystemVerilog.
- Verification insights into random techniques.
- Verification of large scale ASICs.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
- Background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
北京有相关职位吗？
比手机SoC复杂度还高，这种坑不多吧，跳槽很困难吧
前四项都还算简单
第五项是要在soc level上验证NOC?
第六项大部分前端要做的事情不多
比较好奇第七项你也写什么类型的uvc,checker？
另外，不做performance test/stress test?