展讯招CPU相关职位啦！(新增一个职位！）
时间：12-12
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展讯招聘CPU相关职位啦，地点在北京！感兴趣的童鞋可以投递简历至happyeveday86@yeah.net。待遇从优，机会难得。
下面是具体的职位及要求：
(1) CPU design engineer
Responsibilities:
The candidate will participate in the design work of an exciting CPU project. He or she will be responsible for designing of certain block of the CPU, by working closely with modeling, verification, and implementation teams, and deliver the design which meets all functional and performance requirements, and achieve power and area goals.
Qualifications:
1. The ideal candidate should have a MS or higher degree with hands-on CPU design experience.
2. Must have good understanding of the fundamentals of CPU architecture. ARM experience is a big plus.
3. Strong awareness of functionality, performance and physical implementation tradeoffs.
(2) Design verification engineer (emulation)
Responsibilities:
1. The candidate will be responsible for design verification of an exciting CPU project, with the focus on emulation and FPGA.
2. To investigate and implement the methodology of efficient debugging on emulation environment, for example, hybrid environment and cosim, checkpointing, synthesizable SVA, etc.
3. To develop and execute verification plans the top level or SOC level on emulation environment.
Qualifications:
1. The ideal candidate should have a MS or higher degree with hands-on CPU design verification experience.
2. Experiences of one of the mainstream emulation platform is a big plus, for example Cadence’s Palladium, Mentor Graphics’ Veloce, or Synopsys’s Zebu.
3. Experiences of FPGA prototyping is a plus.
4. Experiences of synthesizable SVA is a plus.
5. Low level software knowledge such as uboot or Linux kernel is desired.
6. Be familiar with ARM assembly language is a big plus.
7. Be familiar with ARM tool chain is a plus.
(3) CPU modeling engineer
Responsibilities:
1. The candidate will participate in all modeling work of an exciting CPU project, including performance modeling, ISS modeling, and low-level software.
2. CPU performance modeling and performance analysis.
3. ISS development and possibly ESL integration.
4. Micro-architecture exploration.
Qualifications:
1. The ideal candidate should have a MS or higher degree with hands-on CPU design or modeling experiences.
2. Detailed CPU architecture knowledge. ARM experience is a plus.
3. Fluent in C/C++ and Python/Perl. Knowledge of Verilog/SystemVerilog is a plus.
4. Knowledge of OS and compiler is a plus.
5. Familiar with at least one of the CPU core model framework is desired, for example GEM5, SimpleScalar, or QEMU.
(4) Virtualization software engineer (ARM)
Responsibilities:
The candidate will work in Spreadtrum’s processor division. Working with the design, verification, and performance teams, he or she will focus on the virtualization part of the new ARMv8 architecture, and play an essential role in the whole CPU project process, from very early architecting stage, to late mass production stage.
Qualifications:
1. Extensive software development experience with C/C++ . Linux background is a big plus.
2. Knowledge of low level assembler programming languages. ARM assembler is a big plus.
3. Experience of complex CPU architecture features and their corresponding interactions, especially relating to caches, MMU, SMP, coherency and out of order execution Knowledge of CPU virtualization architecture, preferably on ARM.
4. Experience of developing and debugging low level software at the architectural level
5. Experience of Hypervisor software development such as KVM, XEN or L4 etc.
(5) CPU design and verification tools development
Summary
o New collage graduate or limited working experience is acceptabe..
o Immediate deliverable will be designing and implementation of a Domain Specific Language (DSL)
for writing different assembly language program with architectural features; and a
Test Description Language.
Course work requirement
o Compiler construction courses.
o Operating system internals related to micro-kernel.
o Computer architecture.
o Abstract algebra. Preferably some higher level math courses.
o (optional) Courses related to computer hardware/software security.
下面是具体的职位及要求：
(1) CPU design engineer
Responsibilities:
The candidate will participate in the design work of an exciting CPU project. He or she will be responsible for designing of certain block of the CPU, by working closely with modeling, verification, and implementation teams, and deliver the design which meets all functional and performance requirements, and achieve power and area goals.
Qualifications:
1. The ideal candidate should have a MS or higher degree with hands-on CPU design experience.
2. Must have good understanding of the fundamentals of CPU architecture. ARM experience is a big plus.
3. Strong awareness of functionality, performance and physical implementation tradeoffs.
(2) Design verification engineer (emulation)
Responsibilities:
1. The candidate will be responsible for design verification of an exciting CPU project, with the focus on emulation and FPGA.
2. To investigate and implement the methodology of efficient debugging on emulation environment, for example, hybrid environment and cosim, checkpointing, synthesizable SVA, etc.
3. To develop and execute verification plans the top level or SOC level on emulation environment.
Qualifications:
1. The ideal candidate should have a MS or higher degree with hands-on CPU design verification experience.
2. Experiences of one of the mainstream emulation platform is a big plus, for example Cadence’s Palladium, Mentor Graphics’ Veloce, or Synopsys’s Zebu.
3. Experiences of FPGA prototyping is a plus.
4. Experiences of synthesizable SVA is a plus.
5. Low level software knowledge such as uboot or Linux kernel is desired.
6. Be familiar with ARM assembly language is a big plus.
7. Be familiar with ARM tool chain is a plus.
(3) CPU modeling engineer
Responsibilities:
1. The candidate will participate in all modeling work of an exciting CPU project, including performance modeling, ISS modeling, and low-level software.
2. CPU performance modeling and performance analysis.
3. ISS development and possibly ESL integration.
4. Micro-architecture exploration.
Qualifications:
1. The ideal candidate should have a MS or higher degree with hands-on CPU design or modeling experiences.
2. Detailed CPU architecture knowledge. ARM experience is a plus.
3. Fluent in C/C++ and Python/Perl. Knowledge of Verilog/SystemVerilog is a plus.
4. Knowledge of OS and compiler is a plus.
5. Familiar with at least one of the CPU core model framework is desired, for example GEM5, SimpleScalar, or QEMU.
(4) Virtualization software engineer (ARM)
Responsibilities:
The candidate will work in Spreadtrum’s processor division. Working with the design, verification, and performance teams, he or she will focus on the virtualization part of the new ARMv8 architecture, and play an essential role in the whole CPU project process, from very early architecting stage, to late mass production stage.
Qualifications:
1. Extensive software development experience with C/C++ . Linux background is a big plus.
2. Knowledge of low level assembler programming languages. ARM assembler is a big plus.
3. Experience of complex CPU architecture features and their corresponding interactions, especially relating to caches, MMU, SMP, coherency and out of order execution Knowledge of CPU virtualization architecture, preferably on ARM.
4. Experience of developing and debugging low level software at the architectural level
5. Experience of Hypervisor software development such as KVM, XEN or L4 etc.
(5) CPU design and verification tools development
Summary
o New collage graduate or limited working experience is acceptabe..
o Immediate deliverable will be designing and implementation of a Domain Specific Language (DSL)
for writing different assembly language program with architectural features; and a
Test Description Language.
Course work requirement
o Compiler construction courses.
o Operating system internals related to micro-kernel.
o Computer architecture.
o Abstract algebra. Preferably some higher level math courses.
o (optional) Courses related to computer hardware/software security.