豪威科技，内部推荐职位
时间：12-12
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公司新开两个急招职位，各要4个人，工作地点：上海张江，福利待遇细节问题可以站内咨询。
JD如下：
deo Design Engineer (*4)
Job Description:
* Specify micro-architecture spec for media processors.
* Design logic related to video compression in Verilog and System Verilog.
* Verify design and debug in both RTL-level and gate-level.
* Synthesize and optimize RTL for timing, area and power.
* Perform static timing analysis, formal verification, and clock domain crossing check.
* Participate FPGA debug and bring up chip.
Requirements:
* MSEE/CE with work experience.
* Experience in video compression/decompression is desired.
* Good understanding of computer architecture, logic design, and VLSI design.
* Knowledge of System Verilog, Verilog, C, C++, Perl, and Tcl.
* Strong communication skills and good team player.
Verification engineer(*4)
Position Overview:
On this key position, you will be able to make significant contributions to define the verification scope, develop the verification infrastructure and verify the correctness of the design with your experience and brilliant idea. If you are aiming high and are passionate for challenges, we are cordially inviting you to join the team for the ride.
Responsibilities:
* Develop verification environment, including test bench and regression system creation, embed it in company customized design flow.
* Build test plan and verify the function of design, support gate level functional verification, run coverage and regression. Analyze coverage gaps and devise strategy to fill coverage holes.
* Work closely with different groups to review specification, improve verification plan and methodology, and ensure full test coverage.
* Interfacing EDA vendors for for modern verification methodology, assess vendors' design verification capabilities and convergence .
* Related documentation.
Requirements:
* BSEE with 4+ (or MSEE with 2+) years experience in ASIC verification, complex SOC verification experience is preferred.
* Solid knowledge in verification methodology. Experience in verification using random stimulus along with functional coverage and assertion-based verification method. Experience in UVM/OVM, object oriented design principles, Mentor Questasim SV, lower power verification flow with CPF/UPF.
* Experience in developing block and chip level test benches, test plan creation.
* Good at timing analysis, practical skill with gate-level simulation and debugging techniques.
* Strong script programming skills, such as Shell scripting, Perl and Tcl programming, to develop command scripts.
* Self-motivated to drive for excellence. Must be a team player, and be disciplined and well organized.
* Excellent communication skills, and be able to work under schedule pressure.
公司现在正在谈收购，机会挺好，岗位急招，薪资还不错，有意向的朋友也站内联系，有什么可以咨询我。
JD如下：
deo Design Engineer (*4)
Job Description:
* Specify micro-architecture spec for media processors.
* Design logic related to video compression in Verilog and System Verilog.
* Verify design and debug in both RTL-level and gate-level.
* Synthesize and optimize RTL for timing, area and power.
* Perform static timing analysis, formal verification, and clock domain crossing check.
* Participate FPGA debug and bring up chip.
Requirements:
* MSEE/CE with work experience.
* Experience in video compression/decompression is desired.
* Good understanding of computer architecture, logic design, and VLSI design.
* Knowledge of System Verilog, Verilog, C, C++, Perl, and Tcl.
* Strong communication skills and good team player.
Verification engineer(*4)
Position Overview:
On this key position, you will be able to make significant contributions to define the verification scope, develop the verification infrastructure and verify the correctness of the design with your experience and brilliant idea. If you are aiming high and are passionate for challenges, we are cordially inviting you to join the team for the ride.
Responsibilities:
* Develop verification environment, including test bench and regression system creation, embed it in company customized design flow.
* Build test plan and verify the function of design, support gate level functional verification, run coverage and regression. Analyze coverage gaps and devise strategy to fill coverage holes.
* Work closely with different groups to review specification, improve verification plan and methodology, and ensure full test coverage.
* Interfacing EDA vendors for for modern verification methodology, assess vendors' design verification capabilities and convergence .
* Related documentation.
Requirements:
* BSEE with 4+ (or MSEE with 2+) years experience in ASIC verification, complex SOC verification experience is preferred.
* Solid knowledge in verification methodology. Experience in verification using random stimulus along with functional coverage and assertion-based verification method. Experience in UVM/OVM, object oriented design principles, Mentor Questasim SV, lower power verification flow with CPF/UPF.
* Experience in developing block and chip level test benches, test plan creation.
* Good at timing analysis, practical skill with gate-level simulation and debugging techniques.
* Strong script programming skills, such as Shell scripting, Perl and Tcl programming, to develop command scripts.
* Self-motivated to drive for excellence. Must be a team player, and be disciplined and well organized.
* Excellent communication skills, and be able to work under schedule pressure.
公司现在正在谈收购，机会挺好，岗位急招，薪资还不错，有意向的朋友也站内联系，有什么可以咨询我。
你们本来就是华人老板的伪外企，再说现在已经被国资收购了，基本算民企了。
JD要不弄个中文版的？
工作地点在哪里？
这个……大牛您将就看一下啊，有的专业术语中文可能不好翻译
上海张江乡下，距离地铁站3公里的地方
周边一片荒芜
在上海张江
你好几年没来了吧？
我要是你我就删帖！真的！信哥的话。
几年前我面试过豪威科技，还拿过offer
5轮面试一路面到VP
真没觉得你们技术好到非全英文无法表达的程度
脱离IC好几年了
最近几年都在EDA公司，俯视你们
哦，服侍你们
哪个vp面过你？说来听听？再说ov的面试从来没有5轮这么多。
额，看看有没有朋友感兴趣吧。招人实在困难
那就是你没