我也来发几个NV的职位
时间：12-12
整理：3721RD
点击：
☆─────────────────────────────────────☆
Helix (找不到那个平衡点) 于 (Tue May 26 12:49:57 2009) 提到:
主要有这些，感兴趣的可以先站内联系:)
1. Customer Quality Engineer
2. Physical Design Engineer
3. GPU-ASIC-Physical Design Engineer
4. Graphics Architect
5. ASIC Design Engineer
6. ASIC Verification Engineer
7. Mask Layout Design Engineer
8. 3D Performance Tools Software Engineer
9. QA Software Engineer
Position located in Shanghai:
1. Customer Quality Engineer
Responsibilities:
1. Provide direct technical support with customers on GPU/Motherboard Chipset quality/production issues.
- Assist customers in first level failure analysis (FA) (isolate cause to manufacturing problem, chip problem, hardware, software or test problem) to determine likely cause of quality issues.
- Provide immediate response to customer and quick feedback to NVIDIA when there is a field incidence. Manage and report incidence progress until closure.
- Work with application engineering and sales team to provide technical support and customer service to customers.
- Collect, analyze and report customer yield data. Identify and alert of excursion in yield rates.
2. Manage customer FA requests and responses (status tracking/reporting/documentation)
- Co-work with US team in order to drive corrective actions.
- Monitor corrective actions and continuous improvement activities within the company and / or suppliers.
3. Co-ordinate Factory Audits with other NVIDIA teams
4. Provide technical information and support of RMA process.
MINIMUM REQUIREMENTS:
- Bachelor degree or above (Electronics/Computer Engineering related) .
- Excellent communication skills.
- Experience in customer support.
- Knowledge of GPU/MCP circuit.
- Knowledge of SMT process.
- Verbal and written communication skills in English and Mandarin
2. GPU-ASIC-Physical Design Engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as clocks/timing/convergence/design for test and scripting of flows. You'll be focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES:
- Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
- Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Chip level Integration
- Develop flow to physically partition and floorplan the entire chip.
- Develop and dc-shell scripts for performing ECO's.
MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC design experience ideally with a focus in timing
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environment
- Keep up to date with leading edge technologies
3. GRAPHICS ARCHITECT
RESPONSIBILITIES:
- Design and develop state of the art GPU hardware, in the area of graphics modules, computation units, data communication units, or memory controllers
- Working within a team of graphics architects and ASIC engineers to document, design, develop and verify functional and performance models for NVIDIA's new chips.
- Develop tests, testplans, and testing infrastructure to validate the performance and functional correctness of ASICs modeled in C++, RTL and real silicon.
- Develop tests and tools to collect useful information for 3D graphics performance analysis.
REQUIREMENTS:
- Bachelors degree in CS, EE, or Math. Advanced degrees are helpful.
- Minimum 2 years experience in one of the areas:
Microprocessor architecture design & development
3D graphics drivers (d3d or OpenGL) development
System level programming experience in OS, Compiler, software tools, virtual memory system
- Strong CS background with OS, Compiler, Debugger and system level programming and debugging skills
- Strong C/C++ programming ability. Scripting language (Perl, Python, Ruby) experience is a plus.
- Well organized problem solving capability and communication skills
- Strong software debugging capability and experiences
- Familiar with 3D graphics APIs, d3d or/and OpenGL is a plus
- Proactive, creative and a team player
- Excellent English writing for engineering documentation, English oral well enough to attend meetings
4. PHYSICAL DESIGN ENGINEER
RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets
- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end verification across multiple projects
MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- 4+ years of experience in large VLSI physical design implementation on 0.15u, 0.13u, 90nm, or 65nm technology
- Successful track record of delivering products to production is a must.
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers
- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues
- Working knowledge of deep sub-micron routing issues as they relate to power and timing
- Circuit level comprehension of time critical paths, and spice experience a plus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Sequence (Physical Studio) or Magma
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred
5. ASIC Design Engineer
RESPONSIBILITIES:
- ASIC Design for graphics and video processors.
- Micro-architecture definition; working closely with video / graphics and system architects.
- RTL design, verification, emulation, synthesis, timing, and silicon bring-up.
MINIMUM REQUIREMENTS:
- Senior or Lead ASIC / Logic Design engineers with previous experience in Video, Graphics, Microprocessor Design, SOC design, or Multimedia ASIC design.
- Strong logic design and verification skills.
- Verilog and Synopsys experience required. Primetime experience desirable.
- Display experience
- Programming skills in C and/or PERL.
- Good communication skills and proven ability to work well within a team.
- The ideal candidate will be familiar with all aspects of the frontend ASIC design flow including RTL design, verification, synthesis, and timing analysis
- BS in Electrical Engineering, MS preferred.
6. ASIC Verification Engineer
RESPONSIBILITIES:
- Develop and maintain verification environment at both full chip & unit level
- Develop test cases with direct and random approach
- Responsible for running both RTL & gate level simulation
- DFT verification & misc_test
MINIMUM REQUIREMENTS:
- BSEE/MSEE/BSCS/MSCS with 3+ years of experience in digital circuit/ASIC verification
- Strong problem solving and analytical skills
- Must be proficient in Verilog HDL
- Must be strong in Perl programming, or strong in Python/Ruby programming
- Familiar with DFT (scan insertion, MBIST, JTAG and etc.) is preferred
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
- Working knowledge in C/C++, Makefile
- Verilog PLI experience is a plus
7. Mask Layout Design Engineer
JOB DESCRIPTION / QUALIFICATIONS:
- Perform physical layout for standard cells, embedded SRAM macros and custom modules in deep sub-micron CMOS process.
- Cell level and macro level layout floor-planning
- Layout verification including LVS, DRC and ERC.
- Layout data version control and frame-view generation.
MINIMUM REQUIREMENTS:
- BSEE or equivalent.
- Over 1 year related experience.
- Familiar with Cadence design environment.
- Proficient in physical verification (DRC/LVS) tool.
- knowledge of CMOS transistor devices.
- Knowledge of Unix system and commands.
- Place and Route knowledge a plus.
8. 3D Performance Tools Software Engineer
The 3D Performance Tools Software Engineer will have the primary responsibility to design and implement 3D graphics profiling and debugging applications for the PC, Embedded and Mobile 3D development community. The successful candidate will develop applications that will assist developers with identifying bottlenecks and inconsistencies in their 3D graphics application by exposing Driver and Hardware Performance Counters, and presenting the information in a way can be understood by external developers. By listening to the needs coming from the 3D graphics community, the engineer will provide professional solutions to level out the difficulties arising from the development of high-end 3D graphics application.
- 5+ years of experience in programming. 2+ years master, or 5+ years bachelor
- Strong object oriented programming and methodologies.
- In depth knowledge of at least one 3D graphics API: OpenGL, OpenGL ES or Direct3D.
- Strong mathematic skills.
- C/C++
- Experience in 3D Driver Development is a big plus
9. QA Software Engineer
Job Descriptions:
- Develop and maintain the automation test for cuda developing tools.
- Work with existing test infrastructures, ensure the developed test are running nightly, and review the test output daily. Cooperate with the team to identify issues.
- Work with the QA leader to make reasonable test plan.
- Conduct enough manual testing besides the deployed test automation. Ensure test coverage for each release of the product.
Minimum Requirements:
- BS:2+ years MS+:1+ years in an engineering discipline.
- Programming experience in any of C++, C#, Javascript, Perl and Python.
- Experience in using any of the listed programming language to develop test automation.
- Experience in visual studio.
- Experience in QA for programming tools like compiler, debugger and profiler.
- Experience as a QA role in a released product.
Desired Requirements:
- Experience in parallel scientific computing is a plus;
- Experience in MPI, OpenMP or CUDA is a plus;
- Experience in developing tests for API products is preferred;
- Experience in Linux environments is preferred.
☆─────────────────────────────────────☆
LanYieL (唵嘛呢叭咪吽) 于 (Tue May 26 12:54:29 2009) 提到:
你们最近怎么这么生猛啊，出货量上去了？！
☆─────────────────────────────────────☆
Helix (找不到那个平衡点) 于 (Tue May 26 13:05:20 2009) 提到:
削减成本呗，把职位往中国放。
☆─────────────────────────────────────☆
Torlies (推荐Evernote) 于 (Tue May 26 13:32:40 2009) 提到:
顺便解释一下
Physical Design是通常意义下的后端
GPU-ASIC-Physical Design是专门负责timing
主要有这些，感兴趣的可以先站内联系:)
1. Customer Quality Engineer
2. Physical Design Engineer
3. GPU-ASIC-Physical Design Engineer
4. Graphics Architect
5. ASIC Design Engineer
6. ASIC Verification Engineer
7. Mask Layout Design Engineer
8. 3D Performance Tools Software Engineer
9. QA Software Engineer
Position located in Shanghai:
1. Customer Quality Engineer
Responsibilities:
1. Provide direct technical support with customers on GPU/Motherboard Chipset quality/production issues.
- Assist customers in first level failure analysis (FA) (isolate cause to manufacturing problem, chip problem, hardware, software or test problem) to determine likely cause of quality issues.
- Provide immediate response to customer and quick feedback to NVIDIA when there is a field incidence. Manage and report incidence progress until closure.
- Work with application engineering and sales team to provide technical support and customer service to customers.
- Collect, analyze and report customer yield data. Identify and alert of excursion in yield rates.
2. Manage customer FA requests and responses (status tracking/reporting/documentation)
- Co-work with US team in order to drive corrective actions.
- Monitor corrective actions and continuous improvement activities within the company and / or suppliers.
3. Co-ordinate Factory Audits with other NVIDIA teams
4. Provide technical information and support of RMA process.
MINIMUM REQUIREMENTS:
- Bachelor degree or above (Electronics/Computer Engineering related) .
- Excellent communication skills.
- Experience in customer support.
- Knowledge of GPU/MCP circuit.
- Knowledge of SMT process.
- Verbal and written communication skills in English and Mandarin
2. GPU-ASIC-Physical Design Engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as clocks/timing/convergence/design for test and scripting of flows. You'll be focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES:
- Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
- Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Chip level Integration
- Develop flow to physically partition and floorplan the entire chip.
- Develop and dc-shell scripts for performing ECO's.
MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC design experience ideally with a focus in timing
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environment
- Keep up to date with leading edge technologies
3. GRAPHICS ARCHITECT
RESPONSIBILITIES:
- Design and develop state of the art GPU hardware, in the area of graphics modules, computation units, data communication units, or memory controllers
- Working within a team of graphics architects and ASIC engineers to document, design, develop and verify functional and performance models for NVIDIA's new chips.
- Develop tests, testplans, and testing infrastructure to validate the performance and functional correctness of ASICs modeled in C++, RTL and real silicon.
- Develop tests and tools to collect useful information for 3D graphics performance analysis.
REQUIREMENTS:
- Bachelors degree in CS, EE, or Math. Advanced degrees are helpful.
- Minimum 2 years experience in one of the areas:
Microprocessor architecture design & development
3D graphics drivers (d3d or OpenGL) development
System level programming experience in OS, Compiler, software tools, virtual memory system
- Strong CS background with OS, Compiler, Debugger and system level programming and debugging skills
- Strong C/C++ programming ability. Scripting language (Perl, Python, Ruby) experience is a plus.
- Well organized problem solving capability and communication skills
- Strong software debugging capability and experiences
- Familiar with 3D graphics APIs, d3d or/and OpenGL is a plus
- Proactive, creative and a team player
- Excellent English writing for engineering documentation, English oral well enough to attend meetings
4. PHYSICAL DESIGN ENGINEER
RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets
- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end verification across multiple projects
MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- 4+ years of experience in large VLSI physical design implementation on 0.15u, 0.13u, 90nm, or 65nm technology
- Successful track record of delivering products to production is a must.
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers
- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues
- Working knowledge of deep sub-micron routing issues as they relate to power and timing
- Circuit level comprehension of time critical paths, and spice experience a plus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Sequence (Physical Studio) or Magma
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred
5. ASIC Design Engineer
RESPONSIBILITIES:
- ASIC Design for graphics and video processors.
- Micro-architecture definition; working closely with video / graphics and system architects.
- RTL design, verification, emulation, synthesis, timing, and silicon bring-up.
MINIMUM REQUIREMENTS:
- Senior or Lead ASIC / Logic Design engineers with previous experience in Video, Graphics, Microprocessor Design, SOC design, or Multimedia ASIC design.
- Strong logic design and verification skills.
- Verilog and Synopsys experience required. Primetime experience desirable.
- Display experience
- Programming skills in C and/or PERL.
- Good communication skills and proven ability to work well within a team.
- The ideal candidate will be familiar with all aspects of the frontend ASIC design flow including RTL design, verification, synthesis, and timing analysis
- BS in Electrical Engineering, MS preferred.
6. ASIC Verification Engineer
RESPONSIBILITIES:
- Develop and maintain verification environment at both full chip & unit level
- Develop test cases with direct and random approach
- Responsible for running both RTL & gate level simulation
- DFT verification & misc_test
MINIMUM REQUIREMENTS:
- BSEE/MSEE/BSCS/MSCS with 3+ years of experience in digital circuit/ASIC verification
- Strong problem solving and analytical skills
- Must be proficient in Verilog HDL
- Must be strong in Perl programming, or strong in Python/Ruby programming
- Familiar with DFT (scan insertion, MBIST, JTAG and etc.) is preferred
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
- Working knowledge in C/C++, Makefile
- Verilog PLI experience is a plus
7. Mask Layout Design Engineer
JOB DESCRIPTION / QUALIFICATIONS:
- Perform physical layout for standard cells, embedded SRAM macros and custom modules in deep sub-micron CMOS process.
- Cell level and macro level layout floor-planning
- Layout verification including LVS, DRC and ERC.
- Layout data version control and frame-view generation.
MINIMUM REQUIREMENTS:
- BSEE or equivalent.
- Over 1 year related experience.
- Familiar with Cadence design environment.
- Proficient in physical verification (DRC/LVS) tool.
- knowledge of CMOS transistor devices.
- Knowledge of Unix system and commands.
- Place and Route knowledge a plus.
8. 3D Performance Tools Software Engineer
The 3D Performance Tools Software Engineer will have the primary responsibility to design and implement 3D graphics profiling and debugging applications for the PC, Embedded and Mobile 3D development community. The successful candidate will develop applications that will assist developers with identifying bottlenecks and inconsistencies in their 3D graphics application by exposing Driver and Hardware Performance Counters, and presenting the information in a way can be understood by external developers. By listening to the needs coming from the 3D graphics community, the engineer will provide professional solutions to level out the difficulties arising from the development of high-end 3D graphics application.
- 5+ years of experience in programming. 2+ years master, or 5+ years bachelor
- Strong object oriented programming and methodologies.
- In depth knowledge of at least one 3D graphics API: OpenGL, OpenGL ES or Direct3D.
- Strong mathematic skills.
- C/C++
- Experience in 3D Driver Development is a big plus
9. QA Software Engineer
Job Descriptions:
- Develop and maintain the automation test for cuda developing tools.
- Work with existing test infrastructures, ensure the developed test are running nightly, and review the test output daily. Cooperate with the team to identify issues.
- Work with the QA leader to make reasonable test plan.
- Conduct enough manual testing besides the deployed test automation. Ensure test coverage for each release of the product.
Minimum Requirements:
- BS:2+ years MS+:1+ years in an engineering discipline.
- Programming experience in any of C++, C#, Javascript, Perl and Python.
- Experience in using any of the listed programming language to develop test automation.
- Experience in visual studio.
- Experience in QA for programming tools like compiler, debugger and profiler.
- Experience as a QA role in a released product.
Desired Requirements:
- Experience in parallel scientific computing is a plus;
- Experience in MPI, OpenMP or CUDA is a plus;
- Experience in developing tests for API products is preferred;
- Experience in Linux environments is preferred.
☆─────────────────────────────────────☆
feynman (费曼) 于 (Tue May 26 15:25:15 2009) 提到:
苦死
我又不合适
☆─────────────────────────────────────☆
tonyboz (总是能莫名被疯狗咬上～) 于 (Tue May 26 15:41:45 2009) 提到:
跟o8m同学的政策相悖啊～
☆─────────────────────────────────────☆
eminemshow (DOGGIE) 于 (Tue May 26 15:59:10 2009) 提到:
这个命名颇具混淆性。
☆─────────────────────────────────────☆
microqq (QQ) 于 (Tue May 26 16:24:51 2009) 提到:
哇机会多多啊
☆─────────────────────────────────────☆
lasik (lasik) 于 (Tue May 26 19:09:56 2009) 提到:
MS/5年经验能拿多少钱?
☆─────────────────────────────────────☆
ouzi770 (ouzi770) 于 (Tue May 26 19:27:26 2009) 提到:
同问，税前20w有不
☆─────────────────────────────────────☆
janefeier (Forget it!) 于 (Tue May 26 19:33:57 2009) 提到:
赞！
☆─────────────────────────────────────☆
Torlies (推荐Evernote) 于 (Tue May 26 19:59:47 2009) 提到:
待遇问题大家就不用问了，因为我们也不知道.....只有HR知道
☆─────────────────────────────────────☆
zlzlaaaa (海阔天空·在勇敢以后) 于 (Tue May 26 20:24:25 2009) 提到:
应该可以，NV有米，但不知道这个年头人家肯给不
☆─────────────────────────────────────☆
m8d (8d) 于 (Tue May 26 20:53:46 2009) 提到:
要求好高啊
asic designe engineer要求Senior or Lead ASIC ...
☆─────────────────────────────────────☆
ustc23 (醉生梦死酒) 于 (Tue May 26 21:00:28 2009) 提到:
赞！
☆─────────────────────────────────────☆
fatbig (自摸不息) 于 (Tue May 26 21:13:00 2009) 提到:
你要是知道告诉我一声啊。。
☆─────────────────────────────────────☆
Yew (Yew) 于 (Tue May 26 21:23:03 2009) 提到:
你们做得风生水起的啊
☆─────────────────────────────────────☆
Helix (找不到那个平衡点) 于 (Tue May 26 21:25:09 2009) 提到:
这个还得看和hr谈的怎么样
☆─────────────────────────────────────☆
Torlies (推荐Evernote) 于 (Tue May 26 22:10:51 2009) 提到:
可惜我们不做模拟，不然的话一定把你这种ISSCC灌水大牛连哄带骗搞过来
☆─────────────────────────────────────☆
parachute (Backend Designer) 于 (Tue May 26 22:33:56 2009) 提到:
不错， 看来ic 要恢复了
☆─────────────────────────────────────☆
stoned (2009) 于 (Tue May 26 22:57:02 2009) 提到:
是的，现在foundary的量很猛了
☆─────────────────────────────────────☆
Hoopman (Manu) 于 (Wed May 27 10:32:54 2009) 提到:
有position in beijing么
Helix (找不到那个平衡点) 于 (Tue May 26 12:49:57 2009) 提到:
主要有这些，感兴趣的可以先站内联系:)
1. Customer Quality Engineer
2. Physical Design Engineer
3. GPU-ASIC-Physical Design Engineer
4. Graphics Architect
5. ASIC Design Engineer
6. ASIC Verification Engineer
7. Mask Layout Design Engineer
8. 3D Performance Tools Software Engineer
9. QA Software Engineer
Position located in Shanghai:
1. Customer Quality Engineer
Responsibilities:
1. Provide direct technical support with customers on GPU/Motherboard Chipset quality/production issues.
- Assist customers in first level failure analysis (FA) (isolate cause to manufacturing problem, chip problem, hardware, software or test problem) to determine likely cause of quality issues.
- Provide immediate response to customer and quick feedback to NVIDIA when there is a field incidence. Manage and report incidence progress until closure.
- Work with application engineering and sales team to provide technical support and customer service to customers.
- Collect, analyze and report customer yield data. Identify and alert of excursion in yield rates.
2. Manage customer FA requests and responses (status tracking/reporting/documentation)
- Co-work with US team in order to drive corrective actions.
- Monitor corrective actions and continuous improvement activities within the company and / or suppliers.
3. Co-ordinate Factory Audits with other NVIDIA teams
4. Provide technical information and support of RMA process.
MINIMUM REQUIREMENTS:
- Bachelor degree or above (Electronics/Computer Engineering related) .
- Excellent communication skills.
- Experience in customer support.
- Knowledge of GPU/MCP circuit.
- Knowledge of SMT process.
- Verbal and written communication skills in English and Mandarin
2. GPU-ASIC-Physical Design Engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as clocks/timing/convergence/design for test and scripting of flows. You'll be focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES:
- Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
- Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Chip level Integration
- Develop flow to physically partition and floorplan the entire chip.
- Develop and dc-shell scripts for performing ECO's.
MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC design experience ideally with a focus in timing
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environment
- Keep up to date with leading edge technologies
3. GRAPHICS ARCHITECT
RESPONSIBILITIES:
- Design and develop state of the art GPU hardware, in the area of graphics modules, computation units, data communication units, or memory controllers
- Working within a team of graphics architects and ASIC engineers to document, design, develop and verify functional and performance models for NVIDIA's new chips.
- Develop tests, testplans, and testing infrastructure to validate the performance and functional correctness of ASICs modeled in C++, RTL and real silicon.
- Develop tests and tools to collect useful information for 3D graphics performance analysis.
REQUIREMENTS:
- Bachelors degree in CS, EE, or Math. Advanced degrees are helpful.
- Minimum 2 years experience in one of the areas:
Microprocessor architecture design & development
3D graphics drivers (d3d or OpenGL) development
System level programming experience in OS, Compiler, software tools, virtual memory system
- Strong CS background with OS, Compiler, Debugger and system level programming and debugging skills
- Strong C/C++ programming ability. Scripting language (Perl, Python, Ruby) experience is a plus.
- Well organized problem solving capability and communication skills
- Strong software debugging capability and experiences
- Familiar with 3D graphics APIs, d3d or/and OpenGL is a plus
- Proactive, creative and a team player
- Excellent English writing for engineering documentation, English oral well enough to attend meetings
4. PHYSICAL DESIGN ENGINEER
RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets
- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end verification across multiple projects
MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- 4+ years of experience in large VLSI physical design implementation on 0.15u, 0.13u, 90nm, or 65nm technology
- Successful track record of delivering products to production is a must.
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers
- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues
- Working knowledge of deep sub-micron routing issues as they relate to power and timing
- Circuit level comprehension of time critical paths, and spice experience a plus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Sequence (Physical Studio) or Magma
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred
5. ASIC Design Engineer
RESPONSIBILITIES:
- ASIC Design for graphics and video processors.
- Micro-architecture definition; working closely with video / graphics and system architects.
- RTL design, verification, emulation, synthesis, timing, and silicon bring-up.
MINIMUM REQUIREMENTS:
- Senior or Lead ASIC / Logic Design engineers with previous experience in Video, Graphics, Microprocessor Design, SOC design, or Multimedia ASIC design.
- Strong logic design and verification skills.
- Verilog and Synopsys experience required. Primetime experience desirable.
- Display experience
- Programming skills in C and/or PERL.
- Good communication skills and proven ability to work well within a team.
- The ideal candidate will be familiar with all aspects of the frontend ASIC design flow including RTL design, verification, synthesis, and timing analysis
- BS in Electrical Engineering, MS preferred.
6. ASIC Verification Engineer
RESPONSIBILITIES:
- Develop and maintain verification environment at both full chip & unit level
- Develop test cases with direct and random approach
- Responsible for running both RTL & gate level simulation
- DFT verification & misc_test
MINIMUM REQUIREMENTS:
- BSEE/MSEE/BSCS/MSCS with 3+ years of experience in digital circuit/ASIC verification
- Strong problem solving and analytical skills
- Must be proficient in Verilog HDL
- Must be strong in Perl programming, or strong in Python/Ruby programming
- Familiar with DFT (scan insertion, MBIST, JTAG and etc.) is preferred
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
- Working knowledge in C/C++, Makefile
- Verilog PLI experience is a plus
7. Mask Layout Design Engineer
JOB DESCRIPTION / QUALIFICATIONS:
- Perform physical layout for standard cells, embedded SRAM macros and custom modules in deep sub-micron CMOS process.
- Cell level and macro level layout floor-planning
- Layout verification including LVS, DRC and ERC.
- Layout data version control and frame-view generation.
MINIMUM REQUIREMENTS:
- BSEE or equivalent.
- Over 1 year related experience.
- Familiar with Cadence design environment.
- Proficient in physical verification (DRC/LVS) tool.
- knowledge of CMOS transistor devices.
- Knowledge of Unix system and commands.
- Place and Route knowledge a plus.
8. 3D Performance Tools Software Engineer
The 3D Performance Tools Software Engineer will have the primary responsibility to design and implement 3D graphics profiling and debugging applications for the PC, Embedded and Mobile 3D development community. The successful candidate will develop applications that will assist developers with identifying bottlenecks and inconsistencies in their 3D graphics application by exposing Driver and Hardware Performance Counters, and presenting the information in a way can be understood by external developers. By listening to the needs coming from the 3D graphics community, the engineer will provide professional solutions to level out the difficulties arising from the development of high-end 3D graphics application.
- 5+ years of experience in programming. 2+ years master, or 5+ years bachelor
- Strong object oriented programming and methodologies.
- In depth knowledge of at least one 3D graphics API: OpenGL, OpenGL ES or Direct3D.
- Strong mathematic skills.
- C/C++
- Experience in 3D Driver Development is a big plus
9. QA Software Engineer
Job Descriptions:
- Develop and maintain the automation test for cuda developing tools.
- Work with existing test infrastructures, ensure the developed test are running nightly, and review the test output daily. Cooperate with the team to identify issues.
- Work with the QA leader to make reasonable test plan.
- Conduct enough manual testing besides the deployed test automation. Ensure test coverage for each release of the product.
Minimum Requirements:
- BS:2+ years MS+:1+ years in an engineering discipline.
- Programming experience in any of C++, C#, Javascript, Perl and Python.
- Experience in using any of the listed programming language to develop test automation.
- Experience in visual studio.
- Experience in QA for programming tools like compiler, debugger and profiler.
- Experience as a QA role in a released product.
Desired Requirements:
- Experience in parallel scientific computing is a plus;
- Experience in MPI, OpenMP or CUDA is a plus;
- Experience in developing tests for API products is preferred;
- Experience in Linux environments is preferred.
☆─────────────────────────────────────☆
LanYieL (唵嘛呢叭咪吽) 于 (Tue May 26 12:54:29 2009) 提到:
你们最近怎么这么生猛啊，出货量上去了？！
☆─────────────────────────────────────☆
Helix (找不到那个平衡点) 于 (Tue May 26 13:05:20 2009) 提到:
削减成本呗，把职位往中国放。
☆─────────────────────────────────────☆
Torlies (推荐Evernote) 于 (Tue May 26 13:32:40 2009) 提到:
顺便解释一下
Physical Design是通常意义下的后端
GPU-ASIC-Physical Design是专门负责timing
主要有这些，感兴趣的可以先站内联系:)
1. Customer Quality Engineer
2. Physical Design Engineer
3. GPU-ASIC-Physical Design Engineer
4. Graphics Architect
5. ASIC Design Engineer
6. ASIC Verification Engineer
7. Mask Layout Design Engineer
8. 3D Performance Tools Software Engineer
9. QA Software Engineer
Position located in Shanghai:
1. Customer Quality Engineer
Responsibilities:
1. Provide direct technical support with customers on GPU/Motherboard Chipset quality/production issues.
- Assist customers in first level failure analysis (FA) (isolate cause to manufacturing problem, chip problem, hardware, software or test problem) to determine likely cause of quality issues.
- Provide immediate response to customer and quick feedback to NVIDIA when there is a field incidence. Manage and report incidence progress until closure.
- Work with application engineering and sales team to provide technical support and customer service to customers.
- Collect, analyze and report customer yield data. Identify and alert of excursion in yield rates.
2. Manage customer FA requests and responses (status tracking/reporting/documentation)
- Co-work with US team in order to drive corrective actions.
- Monitor corrective actions and continuous improvement activities within the company and / or suppliers.
3. Co-ordinate Factory Audits with other NVIDIA teams
4. Provide technical information and support of RMA process.
MINIMUM REQUIREMENTS:
- Bachelor degree or above (Electronics/Computer Engineering related) .
- Excellent communication skills.
- Experience in customer support.
- Knowledge of GPU/MCP circuit.
- Knowledge of SMT process.
- Verbal and written communication skills in English and Mandarin
2. GPU-ASIC-Physical Design Engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as clocks/timing/convergence/design for test and scripting of flows. You'll be focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES:
- Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
- Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Chip level Integration
- Develop flow to physically partition and floorplan the entire chip.
- Develop and dc-shell scripts for performing ECO's.
MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC design experience ideally with a focus in timing
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environment
- Keep up to date with leading edge technologies
3. GRAPHICS ARCHITECT
RESPONSIBILITIES:
- Design and develop state of the art GPU hardware, in the area of graphics modules, computation units, data communication units, or memory controllers
- Working within a team of graphics architects and ASIC engineers to document, design, develop and verify functional and performance models for NVIDIA's new chips.
- Develop tests, testplans, and testing infrastructure to validate the performance and functional correctness of ASICs modeled in C++, RTL and real silicon.
- Develop tests and tools to collect useful information for 3D graphics performance analysis.
REQUIREMENTS:
- Bachelors degree in CS, EE, or Math. Advanced degrees are helpful.
- Minimum 2 years experience in one of the areas:
Microprocessor architecture design & development
3D graphics drivers (d3d or OpenGL) development
System level programming experience in OS, Compiler, software tools, virtual memory system
- Strong CS background with OS, Compiler, Debugger and system level programming and debugging skills
- Strong C/C++ programming ability. Scripting language (Perl, Python, Ruby) experience is a plus.
- Well organized problem solving capability and communication skills
- Strong software debugging capability and experiences
- Familiar with 3D graphics APIs, d3d or/and OpenGL is a plus
- Proactive, creative and a team player
- Excellent English writing for engineering documentation, English oral well enough to attend meetings
4. PHYSICAL DESIGN ENGINEER
RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets
- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end verification across multiple projects
MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- 4+ years of experience in large VLSI physical design implementation on 0.15u, 0.13u, 90nm, or 65nm technology
- Successful track record of delivering products to production is a must.
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers
- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues
- Working knowledge of deep sub-micron routing issues as they relate to power and timing
- Circuit level comprehension of time critical paths, and spice experience a plus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Sequence (Physical Studio) or Magma
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred
5. ASIC Design Engineer
RESPONSIBILITIES:
- ASIC Design for graphics and video processors.
- Micro-architecture definition; working closely with video / graphics and system architects.
- RTL design, verification, emulation, synthesis, timing, and silicon bring-up.
MINIMUM REQUIREMENTS:
- Senior or Lead ASIC / Logic Design engineers with previous experience in Video, Graphics, Microprocessor Design, SOC design, or Multimedia ASIC design.
- Strong logic design and verification skills.
- Verilog and Synopsys experience required. Primetime experience desirable.
- Display experience
- Programming skills in C and/or PERL.
- Good communication skills and proven ability to work well within a team.
- The ideal candidate will be familiar with all aspects of the frontend ASIC design flow including RTL design, verification, synthesis, and timing analysis
- BS in Electrical Engineering, MS preferred.
6. ASIC Verification Engineer
RESPONSIBILITIES:
- Develop and maintain verification environment at both full chip & unit level
- Develop test cases with direct and random approach
- Responsible for running both RTL & gate level simulation
- DFT verification & misc_test
MINIMUM REQUIREMENTS:
- BSEE/MSEE/BSCS/MSCS with 3+ years of experience in digital circuit/ASIC verification
- Strong problem solving and analytical skills
- Must be proficient in Verilog HDL
- Must be strong in Perl programming, or strong in Python/Ruby programming
- Familiar with DFT (scan insertion, MBIST, JTAG and etc.) is preferred
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
- Working knowledge in C/C++, Makefile
- Verilog PLI experience is a plus
7. Mask Layout Design Engineer
JOB DESCRIPTION / QUALIFICATIONS:
- Perform physical layout for standard cells, embedded SRAM macros and custom modules in deep sub-micron CMOS process.
- Cell level and macro level layout floor-planning
- Layout verification including LVS, DRC and ERC.
- Layout data version control and frame-view generation.
MINIMUM REQUIREMENTS:
- BSEE or equivalent.
- Over 1 year related experience.
- Familiar with Cadence design environment.
- Proficient in physical verification (DRC/LVS) tool.
- knowledge of CMOS transistor devices.
- Knowledge of Unix system and commands.
- Place and Route knowledge a plus.
8. 3D Performance Tools Software Engineer
The 3D Performance Tools Software Engineer will have the primary responsibility to design and implement 3D graphics profiling and debugging applications for the PC, Embedded and Mobile 3D development community. The successful candidate will develop applications that will assist developers with identifying bottlenecks and inconsistencies in their 3D graphics application by exposing Driver and Hardware Performance Counters, and presenting the information in a way can be understood by external developers. By listening to the needs coming from the 3D graphics community, the engineer will provide professional solutions to level out the difficulties arising from the development of high-end 3D graphics application.
- 5+ years of experience in programming. 2+ years master, or 5+ years bachelor
- Strong object oriented programming and methodologies.
- In depth knowledge of at least one 3D graphics API: OpenGL, OpenGL ES or Direct3D.
- Strong mathematic skills.
- C/C++
- Experience in 3D Driver Development is a big plus
9. QA Software Engineer
Job Descriptions:
- Develop and maintain the automation test for cuda developing tools.
- Work with existing test infrastructures, ensure the developed test are running nightly, and review the test output daily. Cooperate with the team to identify issues.
- Work with the QA leader to make reasonable test plan.
- Conduct enough manual testing besides the deployed test automation. Ensure test coverage for each release of the product.
Minimum Requirements:
- BS:2+ years MS+:1+ years in an engineering discipline.
- Programming experience in any of C++, C#, Javascript, Perl and Python.
- Experience in using any of the listed programming language to develop test automation.
- Experience in visual studio.
- Experience in QA for programming tools like compiler, debugger and profiler.
- Experience as a QA role in a released product.
Desired Requirements:
- Experience in parallel scientific computing is a plus;
- Experience in MPI, OpenMP or CUDA is a plus;
- Experience in developing tests for API products is preferred;
- Experience in Linux environments is preferred.
☆─────────────────────────────────────☆
feynman (费曼) 于 (Tue May 26 15:25:15 2009) 提到:
苦死
我又不合适
☆─────────────────────────────────────☆
tonyboz (总是能莫名被疯狗咬上～) 于 (Tue May 26 15:41:45 2009) 提到:
跟o8m同学的政策相悖啊～
☆─────────────────────────────────────☆
eminemshow (DOGGIE) 于 (Tue May 26 15:59:10 2009) 提到:
这个命名颇具混淆性。
☆─────────────────────────────────────☆
microqq (QQ) 于 (Tue May 26 16:24:51 2009) 提到:
哇机会多多啊
☆─────────────────────────────────────☆
lasik (lasik) 于 (Tue May 26 19:09:56 2009) 提到:
MS/5年经验能拿多少钱?
☆─────────────────────────────────────☆
ouzi770 (ouzi770) 于 (Tue May 26 19:27:26 2009) 提到:
同问，税前20w有不
☆─────────────────────────────────────☆
janefeier (Forget it!) 于 (Tue May 26 19:33:57 2009) 提到:
赞！
☆─────────────────────────────────────☆
Torlies (推荐Evernote) 于 (Tue May 26 19:59:47 2009) 提到:
待遇问题大家就不用问了，因为我们也不知道.....只有HR知道
☆─────────────────────────────────────☆
zlzlaaaa (海阔天空·在勇敢以后) 于 (Tue May 26 20:24:25 2009) 提到:
应该可以，NV有米，但不知道这个年头人家肯给不
☆─────────────────────────────────────☆
m8d (8d) 于 (Tue May 26 20:53:46 2009) 提到:
要求好高啊
asic designe engineer要求Senior or Lead ASIC ...
☆─────────────────────────────────────☆
ustc23 (醉生梦死酒) 于 (Tue May 26 21:00:28 2009) 提到:
赞！
☆─────────────────────────────────────☆
fatbig (自摸不息) 于 (Tue May 26 21:13:00 2009) 提到:
你要是知道告诉我一声啊。。
☆─────────────────────────────────────☆
Yew (Yew) 于 (Tue May 26 21:23:03 2009) 提到:
你们做得风生水起的啊
☆─────────────────────────────────────☆
Helix (找不到那个平衡点) 于 (Tue May 26 21:25:09 2009) 提到:
这个还得看和hr谈的怎么样
☆─────────────────────────────────────☆
Torlies (推荐Evernote) 于 (Tue May 26 22:10:51 2009) 提到:
可惜我们不做模拟，不然的话一定把你这种ISSCC灌水大牛连哄带骗搞过来
☆─────────────────────────────────────☆
parachute (Backend Designer) 于 (Tue May 26 22:33:56 2009) 提到:
不错， 看来ic 要恢复了
☆─────────────────────────────────────☆
stoned (2009) 于 (Tue May 26 22:57:02 2009) 提到:
是的，现在foundary的量很猛了
☆─────────────────────────────────────☆
Hoopman (Manu) 于 (Wed May 27 10:32:54 2009) 提到:
有position in beijing么