芯得职位 模拟 射频 SOC 数字 图像架构算法 @上海 简历发 hr@hi
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芯得职位 模拟 射频 SOC 数字 图像架构算法 @上海 简历发 hr@hi-talent.com
JOB TITLE: IC Design Engineer(RF)
职位：IC设计工程师(射频)
JOB DESCRIPTION:
- RF/analog IC design for tuners and receivers for multi-standard TV’s and other wireless systems
- Design and layout of IC blocks, such as LNA, mixer, VGA/PGA, LPF/BPF, VCO, crystal oscillator, PLL, ADC and DAC
- Simulation of RF and analog circuits and systems in Spectre/SpectreRF and Matlab
- Testing and characterization of IC blocks and chips in lab, and ATE and field environments
- IC process and package evaluation including device modeling and PDK
QUALIFICATION:
- 2 years or above Experience in RF/analog design with MS or PhD in electric and electronic engineering;
- Understanding receiver architectures for multi-standard TV products and other wireless systems;
- Hands-on experiences in design of IC blocks to chip top levels in deep submicron CMOS technologies;
- Proficient with simulation tools (Spectre/SpectreRF) and oversight of layout design;
- Demonstrated ability for characterization of block and chip performances in lab and ATE environments;
- Strong communication skills and also excellence as team player.
Key information:
方向一：射频前端设计，包括LNA（低噪声放大器）、Mixer（混频器）、振荡器等等
JOB TITLE: TM Manager（SOC架构方向）
职位：技术市场经理
JOB DESCRIPTION:
? Marketing survey
1. Collect and study market information, closely track industrial and competitor’s trend
2. Release market research report
? Product study
1. Advanced technology on Television Set/STB and WiFi, etc.
2. Competitor’s chip
3. Relevant industrial specifications
4. Relevant system applications
? New product definition
1. Product Requirement Definition (PRD)
2. Product Engineering Specification
QUALIFICATIONS:
? Common requirement
1. Strong ability of
o learning new technologies fast
o analysis, planning, organization, communication and cooperation
o customer relationship developing
2. MSEE with more than 8 years R&D experiences in SOC Design
3. Fluent in English reading, writing and verbal
Professional requirement
1. The candidate should be a senior SOC Designer ( or System Engineer or Application Engineer) in digital Television SOC field, and have a deep understanding of digital television/STB markets
2. Specializes in DTV SOC system architecture and key blosks, including
? Digital and Anaog frond end
? Audeo/video codec
? Imagination post-processing
? Data and control interface such as DDR2/3, WiFi, Ethernet, HDMI, SD/MMC, I2C, SPI, UART…
? Advanced security
3. Familiar with
? Android/Linux OS as well as software ecosystem
? Network protocol like TCP/UDP/RTP/RTCP/RTSP…
? Multiscreen interactive protocol like DLNA and Miracast…
4. With experience on drafting product engineering spec
JOB TITLE: Video Architecture Engineer
职位：视频架构工程师
JOB DESCRIPTION:
- Work in the area of video architecture, algorithm, and software development.
- Develop video/image compression/decompression/processing algorithm, including lossy and lossless.
- Build software models for algorithm with C/C++/SystemC, and assist with hardware design and verification.
QUALIFICATION:
- Ph. D or MS in signal processing, applied mathematics, computer science, electronic engineering and related discipline with good mathematical knowledge.
- Strong experience in algorithms development in one or some of the following signal processing technologies: digital video hardware or software development; image processing/multimedia design; real-time and embedded system design.
- Experience in some of related fields: video compression; video decompression; image compression; image decompression, video processing, image processing, etc.
- Familiar with video codec standards such as MPEG2 / H.264 / HEVC / VP9, etc.
- Strong software skills in C/C++/SystemC.
- Candidates with academic background or ASIC design experience are a big plus to this position.
Key Word：
Video compression, image compression, lossless compression, video codec, video signal processing, image signal processing
有相关项目经验，偏算法
学校
浙江大学，北京大学，清华大学，同济大学，上海交大，复旦大学，中国科学技术大学, etc
JOB TITLE: Senior device Engineer
职位：高级器件工程师
Job responsibility:
- Development/Check/Retarget of SPICE Models related to all CMOS devices available in a PDK library (MOS, MOSCAP, Inductor, Capacitance, Resistor, Bip, Diode...);
- Work closely with foundry engineers to validate silicon electrical performance;
Qualification:
- MS with minimum of 3-5 years experience in semiconductor industry, PhD preferred;
- Master’s Degree or PhD in a technical field;
- Minimum of 3-5 years experience in a field related to Semiconductor Device Modeling;
- Strong fundamental understanding of semiconductor process technology and analysis methodologies;
- Familiar with CMOS processes, RF device characterization and IC design;
- Development of new active and passive devices for RF CMOS technology;
- Fundamental understanding of SPICE Modeling/CAD/EDA/PDK in general;
- Good data analysis, problem solving, and communication skills;
- Self-motivated, inventive, and resourceful;
The following traits are highly valued:
- Strong experience in simulation tools like Spectre, HSPICE, ELDO, Ultrasim, ... and simulation methodologies;
- Familiar with Cadence Layout tools, Assura DRC/LVS;
- Familiar with DC/AC/RF device characterization equipment (LCR meter, oscilloscope, vector network analyzers) and probe-station;
- Experience with TCAD process and device simulation tools;
- Proficient in scripting languages Matlab/Python/Perl and experience with the Microsoft Office programs;
- Experience with EM Simulation tools (HFSS,...);
- Basic familiarity with UNIX/Linux;
- Strong organizational skills, to manage multiple tasks simultaneously and know how to set priorities according to requirements;
- Excellent verbal and written communication skills;
- Ability to manage complete projects with very limited supervision.
JOB TITLE: IC Design Engineer（display）
职位：IC设计工程师
JOB DESCRIPTION:
- Module-level architecture definition and design；
- Module-level RTL implementation；
- Simulation/Verification at both module level and system level；
- Module-level synthesis and timing analysis；
- Writing design spec and report；
- FPGA/silicon debug on related modules.
QUALIFICATION:
- MSEE with Minimum 2-year experience on digital IC design
- Solid knowledge on digital IC design
- Strong skills of Verilog RTL coding and simulation
- Hands-on experiences on EDA tools, such as Cadence and Synopsys tools
- Familiar with C language
- Relevant experiences on video display are plus
- Hardworking and self-motivated
- A team player
JOB TITLE: IC Design Engineer（Analog)
职位：IC设计工程师（模拟）
JOB DESCRIPTION:
- Design, evaluate and verify high speed CMOS analog circuits.
- Oversee layout and verification activities which include floor plan, LVS and DRC.
- Generate design spec and write design review document
- Engineering lab testing and chip debug
QUALIFICATION:
- MSEE,5 years or above working experience in analog circuit design.
- Good fundamental in device physics, analysis and design of analog / mixed-signal circuits.
- Experience in Verilog, AHDL and/or Matlab.
- Ability to do layout floor plan and provide verification/debugging guidance.
- Solid knowledge of EDA design tools. (Analog artist, spectre, HSPICE and nc-verilog ...)
- Design experience in any of the following areas is preferred: PLL, high-speed I/O’s, transceiver, LV-LP analog design
Key information:
IO、high speed、signal intergrity、PLL、low power、DDR、Memory、Flash-
JOB TITLE: IC Design Engineer（Digital)
职位：IC设计工程师（数字）
JOB DESCRIPTION:
- Micro-architecture definition/writing IC design spec；
- RTL coding for logic modules；
- Simulation/Verification of functionalities at both module level and top level；
- Do module level synthesis / timing analysis；
- Writing complete design/verification reports；
- Silicon debug of the related module functionalities；
- Writing test patterns for production tests.
QUALIFICATION:
- MSEE with minimum 2-year experience of digital design experience;
- Experience on SERDES is preferred;
- Relevant experience in high-speed and low power digital design (Semi-flow: customer layout + ASIC flow) is must;
- Relevant experience in Cadence ICMS/ICFB design environment is must;
- Solid knowledge of digital design building blocks (eg. Data-path, Synchronizer, FIFO...);
- Strong skills of Verilog RTL coding and verification and debug;
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc;
- Relevant experience in DDR interface design is a plus;
- Self-motivated and team player.
Key information:
DDR
JOB TITLE: Senior IC Design Engineer（Digital)
职位：高级IC设计工程师（数字）
Job description:
- Micro-architecture definition/writing IC design spec.
- Model level behavior model built up and RTL coding
- Synchronization and asynchronous digital circuit design
- Simulation/verification of functionalities at both module level and top level
- Script based synthesis & timing analysis on GHz working frequency
- Design/verification report & review meeting holding
- Silicon debug of related model functionalities
- Sampler chip testing
Qualification:
- BSEE with minimum 8-year or MSEE with minimum 5-year experience of digital experience
- Relevant experience in high-speed digital design (Semi-flow: customer layout + ASIC flow) is must
- Solid knowledge of high-speed asynchronous circuit design, family with standard cell architecture and behavior
- Solid knowledge of mixed signal design, digital and analog interface
- Family with low-power-design flow
- Strong skills of Verilog RTL coding, verification and debug
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
- Solid knowledge of documentation of design report
- Relevant experience on telecom timing chip is a plus
- Self-motivated and team player
Key information:
Digital-pll、high speed、asynchronous digital design、DAC、ADC、Sigma-Deita
JOB TITLE: Harware Engineer(WIFI)
职位：硬件应用工程师(WIFI)
工作地点：杭州
岗位职责：
1.Wi-Fi产品相关电路设计。
2. 硬件讯号量测，验证与除错。
3. 客户端Design In应用问题解决，提供客户技术支持， 包含Schematic and PCB Layout review.
职位要求：
1.熟悉OrCAD 和Allegro or PADS ；
2. 5年以上工作经验，具有Wi-Fi相关产品经验。
3.电子，电机相关科系。
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn
JOB TITLE: IC Design Engineer(RF)
职位：IC设计工程师(射频)
JOB DESCRIPTION:
- RF/analog IC design for tuners and receivers for multi-standard TV’s and other wireless systems
- Design and layout of IC blocks, such as LNA, mixer, VGA/PGA, LPF/BPF, VCO, crystal oscillator, PLL, ADC and DAC
- Simulation of RF and analog circuits and systems in Spectre/SpectreRF and Matlab
- Testing and characterization of IC blocks and chips in lab, and ATE and field environments
- IC process and package evaluation including device modeling and PDK
QUALIFICATION:
- 2 years or above Experience in RF/analog design with MS or PhD in electric and electronic engineering;
- Understanding receiver architectures for multi-standard TV products and other wireless systems;
- Hands-on experiences in design of IC blocks to chip top levels in deep submicron CMOS technologies;
- Proficient with simulation tools (Spectre/SpectreRF) and oversight of layout design;
- Demonstrated ability for characterization of block and chip performances in lab and ATE environments;
- Strong communication skills and also excellence as team player.
Key information:
方向一：射频前端设计，包括LNA（低噪声放大器）、Mixer（混频器）、振荡器等等
JOB TITLE: TM Manager（SOC架构方向）
职位：技术市场经理
JOB DESCRIPTION:
? Marketing survey
1. Collect and study market information, closely track industrial and competitor’s trend
2. Release market research report
? Product study
1. Advanced technology on Television Set/STB and WiFi, etc.
2. Competitor’s chip
3. Relevant industrial specifications
4. Relevant system applications
? New product definition
1. Product Requirement Definition (PRD)
2. Product Engineering Specification
QUALIFICATIONS:
? Common requirement
1. Strong ability of
o learning new technologies fast
o analysis, planning, organization, communication and cooperation
o customer relationship developing
2. MSEE with more than 8 years R&D experiences in SOC Design
3. Fluent in English reading, writing and verbal
Professional requirement
1. The candidate should be a senior SOC Designer ( or System Engineer or Application Engineer) in digital Television SOC field, and have a deep understanding of digital television/STB markets
2. Specializes in DTV SOC system architecture and key blosks, including
? Digital and Anaog frond end
? Audeo/video codec
? Imagination post-processing
? Data and control interface such as DDR2/3, WiFi, Ethernet, HDMI, SD/MMC, I2C, SPI, UART…
? Advanced security
3. Familiar with
? Android/Linux OS as well as software ecosystem
? Network protocol like TCP/UDP/RTP/RTCP/RTSP…
? Multiscreen interactive protocol like DLNA and Miracast…
4. With experience on drafting product engineering spec
JOB TITLE: Video Architecture Engineer
职位：视频架构工程师
JOB DESCRIPTION:
- Work in the area of video architecture, algorithm, and software development.
- Develop video/image compression/decompression/processing algorithm, including lossy and lossless.
- Build software models for algorithm with C/C++/SystemC, and assist with hardware design and verification.
QUALIFICATION:
- Ph. D or MS in signal processing, applied mathematics, computer science, electronic engineering and related discipline with good mathematical knowledge.
- Strong experience in algorithms development in one or some of the following signal processing technologies: digital video hardware or software development; image processing/multimedia design; real-time and embedded system design.
- Experience in some of related fields: video compression; video decompression; image compression; image decompression, video processing, image processing, etc.
- Familiar with video codec standards such as MPEG2 / H.264 / HEVC / VP9, etc.
- Strong software skills in C/C++/SystemC.
- Candidates with academic background or ASIC design experience are a big plus to this position.
Key Word：
Video compression, image compression, lossless compression, video codec, video signal processing, image signal processing
有相关项目经验，偏算法
学校
浙江大学，北京大学，清华大学，同济大学，上海交大，复旦大学，中国科学技术大学, etc
JOB TITLE: Senior device Engineer
职位：高级器件工程师
Job responsibility:
- Development/Check/Retarget of SPICE Models related to all CMOS devices available in a PDK library (MOS, MOSCAP, Inductor, Capacitance, Resistor, Bip, Diode...);
- Work closely with foundry engineers to validate silicon electrical performance;
Qualification:
- MS with minimum of 3-5 years experience in semiconductor industry, PhD preferred;
- Master’s Degree or PhD in a technical field;
- Minimum of 3-5 years experience in a field related to Semiconductor Device Modeling;
- Strong fundamental understanding of semiconductor process technology and analysis methodologies;
- Familiar with CMOS processes, RF device characterization and IC design;
- Development of new active and passive devices for RF CMOS technology;
- Fundamental understanding of SPICE Modeling/CAD/EDA/PDK in general;
- Good data analysis, problem solving, and communication skills;
- Self-motivated, inventive, and resourceful;
The following traits are highly valued:
- Strong experience in simulation tools like Spectre, HSPICE, ELDO, Ultrasim, ... and simulation methodologies;
- Familiar with Cadence Layout tools, Assura DRC/LVS;
- Familiar with DC/AC/RF device characterization equipment (LCR meter, oscilloscope, vector network analyzers) and probe-station;
- Experience with TCAD process and device simulation tools;
- Proficient in scripting languages Matlab/Python/Perl and experience with the Microsoft Office programs;
- Experience with EM Simulation tools (HFSS,...);
- Basic familiarity with UNIX/Linux;
- Strong organizational skills, to manage multiple tasks simultaneously and know how to set priorities according to requirements;
- Excellent verbal and written communication skills;
- Ability to manage complete projects with very limited supervision.
JOB TITLE: IC Design Engineer（display）
职位：IC设计工程师
JOB DESCRIPTION:
- Module-level architecture definition and design；
- Module-level RTL implementation；
- Simulation/Verification at both module level and system level；
- Module-level synthesis and timing analysis；
- Writing design spec and report；
- FPGA/silicon debug on related modules.
QUALIFICATION:
- MSEE with Minimum 2-year experience on digital IC design
- Solid knowledge on digital IC design
- Strong skills of Verilog RTL coding and simulation
- Hands-on experiences on EDA tools, such as Cadence and Synopsys tools
- Familiar with C language
- Relevant experiences on video display are plus
- Hardworking and self-motivated
- A team player
JOB TITLE: IC Design Engineer（Analog)
职位：IC设计工程师（模拟）
JOB DESCRIPTION:
- Design, evaluate and verify high speed CMOS analog circuits.
- Oversee layout and verification activities which include floor plan, LVS and DRC.
- Generate design spec and write design review document
- Engineering lab testing and chip debug
QUALIFICATION:
- MSEE,5 years or above working experience in analog circuit design.
- Good fundamental in device physics, analysis and design of analog / mixed-signal circuits.
- Experience in Verilog, AHDL and/or Matlab.
- Ability to do layout floor plan and provide verification/debugging guidance.
- Solid knowledge of EDA design tools. (Analog artist, spectre, HSPICE and nc-verilog ...)
- Design experience in any of the following areas is preferred: PLL, high-speed I/O’s, transceiver, LV-LP analog design
Key information:
IO、high speed、signal intergrity、PLL、low power、DDR、Memory、Flash-
JOB TITLE: IC Design Engineer（Digital)
职位：IC设计工程师（数字）
JOB DESCRIPTION:
- Micro-architecture definition/writing IC design spec；
- RTL coding for logic modules；
- Simulation/Verification of functionalities at both module level and top level；
- Do module level synthesis / timing analysis；
- Writing complete design/verification reports；
- Silicon debug of the related module functionalities；
- Writing test patterns for production tests.
QUALIFICATION:
- MSEE with minimum 2-year experience of digital design experience;
- Experience on SERDES is preferred;
- Relevant experience in high-speed and low power digital design (Semi-flow: customer layout + ASIC flow) is must;
- Relevant experience in Cadence ICMS/ICFB design environment is must;
- Solid knowledge of digital design building blocks (eg. Data-path, Synchronizer, FIFO...);
- Strong skills of Verilog RTL coding and verification and debug;
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc;
- Relevant experience in DDR interface design is a plus;
- Self-motivated and team player.
Key information:
DDR
JOB TITLE: Senior IC Design Engineer（Digital)
职位：高级IC设计工程师（数字）
Job description:
- Micro-architecture definition/writing IC design spec.
- Model level behavior model built up and RTL coding
- Synchronization and asynchronous digital circuit design
- Simulation/verification of functionalities at both module level and top level
- Script based synthesis & timing analysis on GHz working frequency
- Design/verification report & review meeting holding
- Silicon debug of related model functionalities
- Sampler chip testing
Qualification:
- BSEE with minimum 8-year or MSEE with minimum 5-year experience of digital experience
- Relevant experience in high-speed digital design (Semi-flow: customer layout + ASIC flow) is must
- Solid knowledge of high-speed asynchronous circuit design, family with standard cell architecture and behavior
- Solid knowledge of mixed signal design, digital and analog interface
- Family with low-power-design flow
- Strong skills of Verilog RTL coding, verification and debug
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
- Solid knowledge of documentation of design report
- Relevant experience on telecom timing chip is a plus
- Self-motivated and team player
Key information:
Digital-pll、high speed、asynchronous digital design、DAC、ADC、Sigma-Deita
JOB TITLE: Harware Engineer(WIFI)
职位：硬件应用工程师(WIFI)
工作地点：杭州
岗位职责：
1.Wi-Fi产品相关电路设计。
2. 硬件讯号量测，验证与除错。
3. 客户端Design In应用问题解决，提供客户技术支持， 包含Schematic and PCB Layout review.
职位要求：
1.熟悉OrCAD 和Allegro or PADS ；
2. 5年以上工作经验，具有Wi-Fi相关产品经验。
3.电子，电机相关科系。
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn