ASIC 职位，新接的职位，挺一下，简历发HR@hi-talent.net

每次看到你的帖子，心理就想，在标题里面标一下location那么难吗？
哪怕在正文前面标一下也行啊
.13

这是为了保密，比如候选人的简历给我们，我们随便发，对候选人的信息是一种泄露，同理，如果我点名道姓的说某某公司招某某人， 客户公司会觉得泄露他们某些商业动作；
再说了 我北京上海 深圳都有职位，所以我也是根据候选人的location来推荐的；
数字集成电路前端设计工程师Digital IC Frontend Design Engineer
Description:
1. Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
2. Write RTL code for high-speed and multi-clock domain designs.
3. Perform functional verification of designs on block and chip level.
4. Perform synthesis and pre-layout timing closure.
5. Perform the clock domain crossing analysis for the different products lines.
6. Generate the Timing .lib and ATPG package for the different product lines.
7. Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
1. MSEE with 2+ years.
2. Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
3. Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
4. Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
5. Understanding C and Perl programming.
6. Have a fluent oral and good writing English skill.
数字集成电路前端验证工程师 Digital IC Frontend Verification Engineer
Description:
l Develop and execute verification plan
l Develop and maintain verification environment
l Define and implement functional/code coverage plan
l Functional/code coverage analysis
l Run simulation for module and chip level, report and debug together with designer
l Develop/maintain/enhance environment (TB/tools/scripts/flow)
Requirement:
l MSEE with 2+ years.
l Proficient and experienced in SVA verification methodology
l Experienced with hardware verification language (Vera, Systems, SystemVerilog)
l Proficient with Verilog HDL
l Proficient with at least one scripting languages, e.g. Csh, Bash, Perl, Tcl
l Familiar with ASIC design flow
数字集成电路后端设计工程师 Digital IC Backend Design Engineer
Job Description:
· Digital layout design for blocks and chips;
· RTL synthesis and timing analysis;
· Documentation of design procedures;
· Work toward improving efficiency in design procedures and methodologies;
· Communicate effectively with other team members.
Requirements:
· Knowledge of IC design/EDA tools, technical documentation, utilities;
· Knowledge of Shell/Perl/Python script language programming skill in Unix/Linux environment;
· Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills;
· Bachelor degree in EE/CS;
· Good English skills to work in an English language environment.
数字集成电路前端设计高级工程师 Digital IC Frontend Design Engineer（Senior）
Description:
l Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
l Write RTL code for high-speed and multi-clock domain designs.
l Perform functional verification of designs on block and chip level.
l Perform synthesis and pre-layout timing closure.
l Perform the clock domain crossing analysis for the different products lines.
l Generate the Timing .lib and ATPG package for the different product lines.
l Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
l MSEE with 2+ years.
l Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
l Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
l Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
l Understanding C and Perl programming.
l Have a fluent oral and good writing English skill.
数字集成电路前端设计工程师 Digital IC Frontend Design Engineer
Description:
l Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
l Write RTL code for high-speed and multi-clock domain designs.
l Perform functional verification of designs on block and chip level.
l Perform synthesis and pre-layout timing closure.
l Perform the clock domain crossing analysis for the different products lines.
l Generate the Timing .lib and ATPG package for the different product lines.
l Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
l MSEE with 2+ years.
l Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
l Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
l Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
l Understanding C and Perl programming.
l Have a fluent oral and good writing English skill.
数字集成电路后端设计工程师 Digital IC Backend Design Engineer
Job Description:
· Digital layout design for blocks and chips;
· RTL synthesis and timing analysis;
· Documentation of design procedures;
· Work toward improving efficiency in design procedures and methodologies;
· Communicate effectively with other team members.
Requirements:
· Knowledge of IC design/EDA tools, technical documentation, utilities;
· Knowledge of Shell/Perl/Python script language programming skill in Unix/Linux environment;
· Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills;
· Bachelor degree in EE/CS;
· Good English skills to work in an English language environment.
实际工作地点：苏州
贵司有招聘需求的，欢迎和我联系；
如果你和你朋友有需要看工作机会的，发简历给我Jane-Jin@Hi-Talent.net

Best Regards,
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯相会企业管理咨询有限公司
Mob:        15921265928
Skype:      ScarlettJaneJin
E-Mail:      Jane-Jin@Hi-Talent.net
QQ:         1687562641
Blog:        http://blog.sina.com.cn/u/1716864892
Weibo:      http://weibo.com/u/1716864892
Linkedin:    jj_seu@hotmail.com