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The Failure Mechanism of Gate Resistance Testing for Power MOSFET
Shaohui Pan Lunwen He Wei Zhang, D. Wang , L.K.
Dept. of Microelectron., Fudan Univ., Shanghai
This paper appears in: Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Issue Date: 23-26 Oct. 2006
On page(s): 2132 - 2134
Location: Shanghai
Print ISBN: 1-4244-0160-7
INSPEC Accession Number: 9408802
Digital Object Identifier: 10.1109/ICSICT.2006.306638
Date of Current Version: 02 四月 2007
ABSTRACT
The vertical DMOS (double diffused MOSFET) is widely used in power microelectronics, its switching performance is determined mainly by the gate resistance and the input capacitance. Thus a gate resistance testing technique is developed in order to determine its device functionality. In this paper the authors discuss various processes induced device failures, such as the poor interconnect of the poly gate and the metal, the bonding wire, and the etch process, and their impact to the performance and reliability of the devices as well as the in-line testing method used for the performance validation
2. http://ieeexplore.ieee.org/Xplore/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel1%2F55%2F2300%2F00063027.pdf%3Farnumber%3D63027&authDecision=-203
Gate-resistance-limited switching frequencies of power MOSFETs
Shenai, K.
General. Electric Co., Schenectady, NY
This paper appears in: Electron Device Letters, IEEE
Issue Date: Nov 1990
Volume: 11 Issue: 11
On page(s): 544 - 546
ISSN: 0741-3106
Cited by: 5
INSPEC Accession Number: 3826007
Digital Object Identifier: 10.1109/55.63027
Date of Current Version: 06 八月 2002
ABSTRACT
High-frequency switching limitation of a power MOSFET resulting from large gate resistance is studied. It is shown that a maximum gate switching frequency can be identified to minimize resistive power dissipation in the gate. Power MOSFETs with refractory silicide gates are shown to result in more than a fivefold improvement in this frequency compared to conventional heavily POCl3-doped polysilicon-gated MOSFETs with metal gate runners
The Failure Mechanism of Gate Resistance Testing for Power MOSFET
Shaohui Pan Lunwen He Wei Zhang, D. Wang , L.K.
Dept. of Microelectron., Fudan Univ., Shanghai
This paper appears in: Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Issue Date: 23-26 Oct. 2006
On page(s): 2132 - 2134
Location: Shanghai
Print ISBN: 1-4244-0160-7
INSPEC Accession Number: 9408802
Digital Object Identifier: 10.1109/ICSICT.2006.306638
Date of Current Version: 02 四月 2007
ABSTRACT
The vertical DMOS (double diffused MOSFET) is widely used in power microelectronics, its switching performance is determined mainly by the gate resistance and the input capacitance. Thus a gate resistance testing technique is developed in order to determine its device functionality. In this paper the authors discuss various processes induced device failures, such as the poor interconnect of the poly gate and the metal, the bonding wire, and the etch process, and their impact to the performance and reliability of the devices as well as the in-line testing method used for the performance validation
2. http://ieeexplore.ieee.org/Xplore/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel1%2F55%2F2300%2F00063027.pdf%3Farnumber%3D63027&authDecision=-203
Gate-resistance-limited switching frequencies of power MOSFETs
Shenai, K.
General. Electric Co., Schenectady, NY
This paper appears in: Electron Device Letters, IEEE
Issue Date: Nov 1990
Volume: 11 Issue: 11
On page(s): 544 - 546
ISSN: 0741-3106
Cited by: 5
INSPEC Accession Number: 3826007
Digital Object Identifier: 10.1109/55.63027
Date of Current Version: 06 八月 2002
ABSTRACT
High-frequency switching limitation of a power MOSFET resulting from large gate resistance is studied. It is shown that a maximum gate switching frequency can be identified to minimize resistive power dissipation in the gate. Power MOSFETs with refractory silicide gates are shown to result in more than a fivefold improvement in this frequency compared to conventional heavily POCl3-doped polysilicon-gated MOSFETs with metal gate runners
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