How do we make trigger signal in verilog？

Hi！
I think this is a basic question but I hope you can help me.
For example, I have a signal DONE that will be high for a certain time for 1 clock cycle. How can I create a signal that is same with DONE and will occur exactly after DONE and also 1 clock cycle.
Thank you.

always@（posedge clk)
begin
    done_dly <= done;
end