Xilinx ISE官方IP可以解密源码了
我有这个需求。怎么联系你，留个联系方式?谢谢！
你好，报个价格
报个价啊
有需要+Q：5523785
这个很容易还来卖钱。 基本原理是在libisl_iostream找到RSA的私钥解出AES密钥，就可以用这个解出内容。
调用openssl的crypt库编程不超过100行。 看我的vivado can_V5_0.vhd这个文件如下
---------------------------------------------------
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------------------------------------------------------------------------
-- Generated by XCC2VHDL IP-XACT conversion v1.2
library ieee;
use ieee.std_logic_1164.all;
library can_v5_0;
use can_v5_0.all;
entity can_v5_0 is
generic (
c_can_rx_dpth : integer := 64;
c_can_tx_dpth : integer := 64;
c_can_num_acf : integer := 4;
c_c2s_mtbf_stages : integer := 2;
c_s2c_mtbf_stages : integer := 2;
c_s_axi_addr_width : integer := 8;
c_s_axi_data_width : integer := 32;
c_family : string := "virtex7"
);
port (
can_clk : in std_logic := '0';
can_phy_rx : in std_logic := '0';
can_phy_tx : out std_logic;
ip2bus_intrevent : out std_logic;
s_axi_aclk : in std_logic := '0';
s_axi_aresetn : in std_logic := '0';
--s_axi_awaddr : in std_logic_vector(c_s_axi_addr_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
--s_axi_wdata : in std_logic_vector(c_s_axi_data_width - 1 downto 0) := (others => '0');
s_axi_wdata : in std_logic_vector(32 - 1 downto 0) := (others => '0');
--s_axi_wstrb : in std_logic_vector((c_s_axi_data_width / 8 ) - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector((32 / 8 ) - 1 downto 0) := (others => '0');
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
--s_axi_araddr : in std_logic_vector(c_s_axi_addr_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
--s_axi_rdata : out std_logic_vector(c_s_axi_data_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(32 - 1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0'
);
end entity can_v5_0;
architecture xilinx of can_v5_0 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes";
constant eval_tic_ps : integer := 10000;
begin
core_options : if true generate
begin cantop_i : entity can_top
generic map (
c_can_rx_dpth => c_can_rx_dpth,
c_can_tx_dpth => c_can_tx_dpth,
c_can_num_acf => c_can_num_acf,
c_c2s_mtbf_stages => c_c2s_mtbf_stages,
c_s2c_mtbf_stages => c_s2c_mtbf_stages,
c_s_axi_addr_width => c_s_axi_addr_width,
c_s_axi_data_width => c_s_axi_data_width,
c_family => c_family
)
port map (
can_clk => can_clk,
can_phy_rx => can_phy_rx,
can_phy_tx => can_phy_tx,
ip2bus_intrevent => ip2bus_intrevent,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
end generate core_options;
end architecture xilinx;
这个是ise的ip和vivado的不一样
由于libisl_iostream.dll加了他们自己的壳，需要先脱壳，后看到他们也是用的openssl库。 不想脱壳可以用Cadence,mentor,synopsys的程序找私钥，一样的过程可以得到 AES密钥
这个横好的建议！
请问，用什么工具脱壳呢?
RSA的私钥(n,d)中，n和d分别有多少byte?RSA密文有多少byte?AES的秘钥和初始向量是在同一RSA密文中，还是2个密文?
这个很给力啊
请问，用什么工具脱壳呢?
在吗 方便留个联系方式吗 有合作 想私聊 看到的 烦请回复
怎么跟你联系呢 ?有需求，加QQ：416808018
大牛，可否请教下解密的相关的?
灌水，升级
试了一下xilinx的 ise、 vivado 和altera的quartus软件自带的IPcore（压缩的和不压缩的）好像都可以得到源码
Lattice 没有装，应该也可以得到吧
黑科技。留个名。MARK一个。
Xilinx & Altera Synopsys 加密IP 还原出源代码
我不收费的！
加QQ： 172346149
基于以上原理，VIVADO2017.2也是可以解出的：
------------------------------------------------------------------------
-- Filename : can_top.vhd
-- Version : 1.00.a
-- Author :
-- Company : Xilinx
-- Description : Top level design, instantiates IPIF and top module for CAN core.
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- can_top.vhd
-- -- cantop.vhd
-- -- can_tl_top.vhd
-- -- can_tl_synch.vhd
-- -- can_tl_clkdiv.vhd
-- -- can_tl_om.vhd
-- -- can_tl_bsp.vhd
-- -- can_tl_arbit.vhd
-- -- can_tl_btl.vhd
-- -- can_tl_acf.vhd
-- -- can_ol_top.vhd
-- -- can_txfifo_cntl_gen.vhd
-- -- can_ol_fifopriority.vhd
-- -- can_tl_arbchk.vhd
-- -- can_rxfifo_cntl_gen.vhd
-- -- can_ol_synch.vhd
-- -- can_ic_main.vhd
-- -- can_bram.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library can_v5_0_16;
use can_v5_0_16.proc_common_pkg.all;
use can_v5_0_16.ipif_pkg.all;
--------------------------------------------------------------------------------
-- Entity section
--------------------------------------------------------------------------------
entity can_top is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_CAN_RX_DPTH : integer := 64;
C_CAN_TX_DPTH : integer := 64;
C_CAN_NUM_ACF : integer := 4;
C_S2C_MTBF_STAGES : integer := 2; -- Number of MTBF Stages for System to
-- CAN CLK Crossing.
C_C2S_MTBF_STAGES : integer := 2; -- Number of MTBF Stages for CAN to
-- System CLK Crossing.
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- axi lite ipif block generics
C_S_AXI_ADDR_WIDTH : integer := 8;
C_S_AXI_DATA_WIDTH : integer := 32;
C_FAMILY : string := "virtex7"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CAN_CLK : in std_logic;
CAN_PHY_RX : in std_logic;
CAN_PHY_TX : out std_logic;
IP2Bus_IntrEvent : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- AXI interface signals
S_AXI_AWADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector ((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute SIGIS of IP2Bus_IntrEvent : signal is "INTR_EDGE_RISING";
--------------------------------------------------------------------------
-- IP licensing section
--------------------------------------------------------------------------
attribute check_license : string;
都是大牛水平呀
学习了，学习了，学习了，
能高速如何破解的吗，跪求