Verilog里面的乘法、求模、除法
时间：10-02
整理：3721RD
点击：
请问这三个运算是如何实现的?是调用FPGA内部已经有的硬件运算单元吗?自己写的乘法器跟直接用*做乘法有什么区别?
这个基本都是LUT，相当于一个ram，两个乘数因子构成地址，一个时钟就能输出
如果你自己写个乘法器，再怎么处理你看多少时钟周期才能输出
There are many ways to implement a multiplier or a divider. If you have small operand size (for example, 8bit) then you can probably do that with LUT that store all possible outcomes in a ROM. however, if you have big operand size (for example, 32bit) then you might need a good algorithm to do that. A popular circuit synthesizer (for example, DC) has already implemented optimized algorithms in its database and you don't have to implement your own. Just write * or / in your RTL will do.
Are you kidding me?