VHDL中的signal定义成了real型不能综合了！怎么改掉啊？
在调试时，我需要的是一个八位输入八位输出的滤波器。如果需要的话，回复我把程序贴上。
贴上来给大家看看啊
咳咳。其实我刚发现可以贴源码的功能。下面就是程序了，是由matlab直接生成的。其中的所有real型signal都没法综合。
-- -------------------------------------------------------------
--
-- Module: test
--
-- Generated by MATLAB(R) 7.5 and the Filter Design HDL Coder 2.1.
--
-- Generated on: 2013-07-25 10:27:24
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- CoeffMultipliers: csd
-- TargetDirectory: D:\Docchang\allsourse\elec\matlab\test
-- Name: test
-- TestBenchStimulus: chirp impulse noise ramp step
--
-- Filter Settings:
--
-- Discrete-Time FIR Filter (real)
-- -------------------------------
-- Filter Structure : Direct-Form FIR
-- Filter Length : 14
-- Stable : Yes
-- Linear Phase : Yes (Type 2)
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY test IS
PORT( clk : IN std_logic;
clk_enable : IN std_logic;
reset : IN std_logic;
filter_in : IN real; -- double
filter_out : OUT real -- double
);
END test;
----------------------------------------------------------------
--Module Architecture: test
----------------------------------------------------------------
ARCHITECTURE rtl OF test IS
-- Local Functions
-- Type Definitions
TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF real; -- double
-- Constants
CONSTANT coeff1 : real := 1.2445673428326549E-004; -- double
CONSTANT coeff2 : real := 1.2086777484162647E-003; -- double
CONSTANT coeff3 : real := -5.5319399142300645E-003; -- double
CONSTANT coeff4 : real := -2.7459709424806123E-002; -- double
CONSTANT coeff5 : real := 8.8802565866896452E-018; -- double
CONSTANT coeff6 : real := 1.6556310718669850E-001; -- double
CONSTANT coeff7 : real := 3.6609540766963811E-001; -- double
CONSTANT coeff8 : real := 3.6609540766963811E-001; -- double
CONSTANT coeff9 : real := 1.6556310718669850E-001; -- double
CONSTANT coeff10 : real := 8.8802565866896452E-018; -- double
CONSTANT coeff11 : real := -2.7459709424806123E-002; -- double
CONSTANT coeff12 : real := -5.5319399142300645E-003; -- double
CONSTANT coeff13 : real := 1.2086777484162647E-003; -- double
CONSTANT coeff14 : real := 1.2445673428326549E-004; -- double
-- Signals
SIGNAL delay_pipeline : delay_pipeline_type(0 TO 13) := (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); -- double
SIGNAL product14 : real := 0.0; -- double
SIGNAL product13 : real := 0.0; -- double
SIGNAL product12 : real := 0.0; -- double
SIGNAL product11 : real := 0.0; -- double
SIGNAL product10 : real := 0.0; -- double
SIGNAL product9 : real := 0.0; -- double
SIGNAL product8 : real := 0.0; -- double
SIGNAL product7 : real := 0.0; -- double
SIGNAL product6 : real := 0.0; -- double
SIGNAL product5 : real := 0.0; -- double
SIGNAL product4 : real := 0.0; -- double
SIGNAL product3 : real := 0.0; -- double
SIGNAL product2 : real := 0.0; -- double
SIGNAL product1 : real := 0.0; -- double
SIGNAL sum1 : real := 0.0; -- double
SIGNAL sum2 : real := 0.0; -- double
SIGNAL sum3 : real := 0.0; -- double
SIGNAL sum4 : real := 0.0; -- double
SIGNAL sum5 : real := 0.0; -- double
SIGNAL sum6 : real := 0.0; -- double
SIGNAL sum7 : real := 0.0; -- double
SIGNAL sum8 : real := 0.0; -- double
SIGNAL sum9 A : real := 0.0; -- double
SIGNAL sum10 : real := 0.0; -- double
SIGNAL sum11 : real := 0.0; -- double
SIGNAL sum12 : real := 0.0; -- double
SIGNAL sum13 : real := 0.0; -- double
SIGNAL output_register : real := 0.0; -- double
BEGIN
-- Block Statements
Delay_Pipeline_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
delay_pipeline(0 TO 13) <= (OTHERS => 0.0000000000000000E+000);
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
delay_pipeline(0) <= filter_in;
delay_pipeline(1 TO 13) <= delay_pipeline(0 TO 12);
END IF;
END IF;
END PROCESS Delay_Pipeline_process;
product14 <= delay_pipeline(13) * coeff14;
product13 <= delay_pipeline(12) * coeff13;
product12 <= delay_pipeline(11) * coeff12;
product11 <= delay_pipeline(10) * coeff11;
product10 <= delay_pipeline(9) * coeff10;
product9 <= delay_pipeline(8) * coeff9;
product8 <= delay_pipeline(7) * coeff8;
product7 <= delay_pipeline(6) * coeff7;
product6 <= delay_pipeline(5) * coeff6;
product5 <= delay_pipeline(4) * coeff5;
product4 <= delay_pipeline(3) * coeff4;
product3 <= delay_pipeline(2) * coeff3;
product2 <= delay_pipeline(1) * coeff2;
product1 <= delay_pipeline(0) * coeff1;
sum1 <= product1 + product2;
sum2 <= sum1 + product3;
sum3 <= sum2 + product4;
sum4 <= sum3 + product5;
sum5 <= sum4 + product6;
sum6 <= sum5 + product7;
sum7 <= sum6 + product8;
sum8 <= sum7 + product9;
sum9 <= sum8 + product10;
sum10 <= sum9 + product11;
sum11 <= sum10 + product12;
sum12 <= sum11 + product13;
sum13 <= sum12 + product14;
Output_Register_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
output_register <= 0.0000000000000000E+000;
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
output_register <= sum13;
END IF;
END IF;
END PROCESS Output_Register_process;
-- Assignment Statements
filter_out <= output_register;
END rtl;
real只能仿真。
只能全部转成2进制的形式，计算的话用查表或者ip core
非常感谢您的回答，但是还有一些问题：
程序里面大部分的real型参数都是小于一的数，而且很不整齐，要怎么转成二进制呢?就是滤波器里的各个参数要怎么处理?要先放大然后移位回去么?以前看到过一个滤波器的程序，他自己做了一个乘法器，但是我不明白即使有了乘法器，要乘的数是一个0.0几的数要怎么乘啊?
小编，不知道你的问题解决了吗?HDL coder 好用吗，数据可综合吗?只能针对Simulink吗，对于M code可以转换吗
遇到了同样问题，
贴上来给大家看看啊
贴上来给大家看看啊