求助VCS的使用
时间：10-02
整理：3721RD
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如题，按照《Verilog 数字VLSI设计教程》的lab1练习vcs的使用，但是出现如下问题，求教各位大神指导！
1 error Source info: `include "../../VCS/Extras.inc" "./TestBench.v", 24 Please fix above issue and compile again. such file or directory'. Source file "../../VCS/Extras.inc" cannot be opened for reading due to 'No Error-[SFCOR] Source file cannot be openedParsing design file './TestBench.v'
1 error Source info: `include "../../VCS/Extras.inc" "./TestBench.v", 24 Please fix above issue and compile again. such file or directory'. Source file "../../VCS/Extras.inc" cannot be opened for reading due to 'No Error-[SFCOR] Source file cannot be openedParsing design file './TestBench.v'
没有这个文件“../../VCS/Extras.inc”
路径不对啊
TestBench.v中include的那个文件不要添加路径例如：
`include "../../VCS/Extras.inc"修改成
`include "Extras.inc"
编译的时候添加：
+incidr+../../VCS
即可，注意相对路径，是相对你的当前工作目录。