viretex5 DCM时钟问题，请大家帮帮忙！
时钟源：clk=24.576MHz
以下是我的代码：
ibufg（
I(clk),
O(clkbuf)
);
dcm(
CLKIN_IN(clkbuf),
CLKFX_OUT(clk32m),
CLK0_OUT(open),
LOCKED_OUT(lock)
);
clk32m_out<=clk32m; --时钟输出管脚
DCM无论采用内部或者外部时钟源，用ISE编译的时候都会出现以下错误：
ERROR:NgdBuild:770 - IBUFG 'CLKIN_IBUFG_INST' and BUFG 'U_IBUFG' on net
'clkbuf' are lined up in series. Buffers of the same direction cannot be
placed in series.
ERROR:NgdBuild:924 - input pad net 'clkbuf' is driving non-buffer
当我将时钟输出屏蔽掉后，程序就能编译成功。
请各位大虾帮帮忙，看看怎么解决掉这个问题。
把ibufg 'U_IBUFG' 去掉，DCM里面可能已经包含了ibufg 'CLKIN_IBUFG_INST'
我将DCM中的ibufg 'CLKIN_IBUFG_INST'去掉，或者将DCM前的ibufg去掉，编译的结果还是一样的。
ERROR:NgdBuild:770 ERROR:NgdBuild:924
点击这两个ERROR，应该可以找到Xilinx更详细的帮助，仔细看看是什么地方用法有误。
你的DCM是用ISE的core generator生成的吗，最好别自己手写。
你用CLK0做为时钟输出就好了。
现在用vhdl的挺多的啊。
先谢谢各位了，我是用ISE的core generator生成的DCM，然后例化的。后来在调试中发现只要将输出信号clk32m_out屏蔽掉编译就OK了。麻烦大家在帮帮忙
请问一下，如何将dcm中的输出bufg去掉，在生长IP核的时候，发现无法将输出bufg去掉，我在生长的dcm。vhdl中自己手动将程序里的输出bufg去掉，程序无法编译。
10.1/11.x NGDBuild - "ERROR:NgdBuild:770..."
FeedbackPrintAR# 34771 Search For Another Answer
Topic NGDBuild
Last Updated 06/01/2010
Status Active
Description
There is a black-box submodule in the design which is fed with an EDIF/NGC netlist. The following errors and warnings are issued during Translate:
"ERROR:NgdBuild:770 - IBUF 'b_IBUF' and IBUF 'b_ibuf' on net 'b_IBUF' are lined up in series. Buffers of the same direction cannot be placed in series.
WARNING:NgdBuild:463 - input pad net 'b_IBUF' has an illegal input buffer
ERROR:NgdBuild:925 - input net 'b_IBUF' is connected to the incorrect side of buffer(s):
pin O on block b_IBUF with type IBUF
ERROR:NgdBuild:924 - input pad net 'clk_BUFGP' is driving non-buffer primitives:
pin C on block h with type FDR, pin C on block g with type FD, pin O on block clk_BUFGP/BUFG with type BUFG
ERROR:NgdBuild:809 - output pad net 'e' has an illegal load:
pin I1 on block Mxor_g_xor0000_Result1 with type LUT2
ERROR:NgdBuild:455 - logical net 'h' has multiple driver(s):
pin Q on block h with type FDR, pin PAD on block h.PAD with type PAD"
How can I resolve these errors?
Solution
These errors are issued because the submodule EDIF/NGC netlist contains IBUFs/OBUFs. XST also adds IBUFs and OBUFs to the top level, so that they are lined up or the pads are driving/being driven by non-buffer components.
When an EDIF/NGC netlist is used as a submodule of another design, the following conditions must be met:
If the input/output ports of the submodule are connected to the top module ports directly, like port1 in the following figure, the IBUFs/OBUFs can be put in the submodule, but the XST property "Read Cores" has to be checked. Then, XST will read the netlist in the project directory or a location specified in "Cores Search Directories" and will not add extra IBUFs/OBUFs on these top level ports.
If the input/output ports of the submodule are NOT connected to the top module ports directly, like port2 in the following figure, the IBUFs/OBUFs must not be put in the submodule.
The following are some solutions to this problem.
Disable IBUF/OBUF insertion when you generate the submodule netlist. Add all IBUFs/OBUFs to the top level.
For XST, go to Synthesis Properties -> Xilinx Specific Options -> uncheck "Add I/O Buffers"
For Synplify Pro, go to Implementation Options -> Device tab -> check "Disable I/O Insertion"
Selectively disable IBUF/OBUF insertion on the input/output ports that are NOT connected to the top module ports directly.
For XST, use "buffer_type" constraint. Please refer to XST User Guide.
For Synplify Pro, refer to (Xilinx Answer 4508).
If the IBUF/OBUFs are instantiated in the submodule, disabling IBUF/OBUF insertion does not remove the buffers from the submodule. If this is the case, remove the IBUF/OBUFs instantaiation from the submodule and instantiate them in the top level.
http://www.xilinx.com/support/answers/34771.htm
看看官方的solution，你写的东西你自己最明白，好好看看那个地方不符合规则
我也遇到了类似的问题，在解决中
看官方论坛
小编找到解决办法没?
把前面bufg去掉，DCM里面已经有bufg了，两个bufg串联导致的?
你这例化的名字都没有?
ibufg ibufg_inst（
I(clk),
O(clkbuf)
);
dcm dcm_inst(
CLKIN_IN(clkbuf),
CLKFX_OUT(clk32m),
CLK0_OUT(open),
LOCKED_OUT(lock)
);
加上例化名试试