输入端口激励问题，跪求
代码，仿真波形放出了，你这样写，看不懂
哎。代码太大，而且我们不能把它放网上，门级网表也很大，3M，放了也没意义。其实我问的就是，为什么直接对代码测试能通过，对综合出的门级网表测试就通不过。
是不是由于你的组合逻辑delay太长导致的，前仿真是仿不出问题的，门级仿真加了延时导致跑不过
这应该由SDC保证，看看综合结果有没有timing violation
在我看来，属于时序约束问题，不知道各位大神怎么看。
大神。我是初学者。dc脚本应该没加计算延时，因为没生成sdf。我们期望的是将代码加入一种逻辑，然后综合成网表。
综合后的文件夹里面只有.mr 和.syn文件，还有生成的_syn.v文件。
以下是脚本。哪位大神帮我看看好吗。我是初学者，脚本是别人写的，我想知道是综合后确实发生了门级延时，但没生成sdf文件，还是这种综合只是不考虑延时的一种“理想网表”
###################################### Current Design: TOP1553
# Load up design files
# uncomment one of the following
#analyze -format verilog TOP1553.v
analyze -format vhdl {if1553.vhd sysreg.vhd fifo.vhd transmitter.vhd rt1553.vhd receiver.vhd encode10m.vhd encode.vhd dpram.vhd decode10m.vhd decode.vhd TOP1553.vhd}
# Tell dc_shell the name of the top level module
elaborate TOP1553
# set a clock
create_clock {ext_clk clk}
# Check for warnings/errorsa
check_design -multiple_designs
# ungroup everything
ungroup -flatten -all
# flatten it all, this forces all the hierarchy to be flattened out
set_flatten true -effort high
uniquify
# compile the design
compile_ultra -area_high_effort_script
#compile_ultra -timing_high_effort_script
#compile_ultra
# Now that the compile is complete report on the results
report_area
report_timing
report_power
############################### begin: renaming section
# remove the following renaming section when not needed
# define the name rules for rename
define_name_rules verilog -remove_port_bus
define_name_rules verilog -remove_internal_net_bus
# name rule for nets
define_name_rules verilog -type net -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9 N" \
-replacement_char "_" \
-prefix "n"
# name rule for cells
define_name_rules verilog -type cell -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9" \
-replacement_char "_" \
-prefix "u"
# name rule for ports
define_name_rules verilog -type port -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9" \
-replacement_char "_" \
-prefix "p"
# change names of variables
change_names -rule verilog -hierarchy
################################ end: renaming section
# Write out the design
write -f verilog TOP1553 -output TOP1553_syn.v
remove_design -all
exit
create_clock {ext_clk clk} //太简单了，我写个大体示例
create_clock -period 10 -name clk [get_port clk] //时钟频率一定要定义
set_clock_uncertainty xxxx [get_clk clk]
set_input_delay 1.7 -clock clk {input signal list}
set_output_delay 1.0 -clock clk {output signal list}
还有对reset 的约束， false-path， multi-cycle 等到。
# Now that the compile is complete report on the results
report_area
report_timing
report_power
write_sdf xxxx.sdf //把sdf 生成出来，在仿真的时候load进去
谢谢大神，我试试。对了，我们那个脚本看来是没有定义输入延时和输出延时，那么就是说我们的脚本出来的就是理想情况，零延时了?
那咋就仿真不通呢。
后仿需要load sdf,你先生成出来，再反标回去
大神，我们的代码综合出来的网表还有个问题和sdf文件不匹配比如 reg [2:0] data 综合出来后就是data_0_,data_1_,data_2_,这样的格式，然后sdf里面要求的是data_reg[0],data_reg[1]这样的
请问什么语句是给内部端口命名的希望改成sdf文件匹配的，我把脚本再给您粘贴一下。麻烦了，指点小白
###################################### Current Design: TOP1553
# Load up design files
# uncomment one of the following
#analyze -format verilog TOP1553.v
analyze -format vhdl {if1553.vhd sysreg.vhd fifo.vhd transmitter.vhd rt1553.vhd receiver.vhd encode10m.vhd encode.vhd dpram.vhd decode10m.vhd decode.vhd TOP1553.vhd}
# Tell dc_shell the name of the top level module
elaborate TOP1553
# set a clock
create_clock {ext_clk clk}
# Check for warnings/errorsa
check_design -multiple_designs
# ungroup everything
ungroup -flatten -all
# flatten it all, this forces all the hierarchy to be flattened out
set_flatten true -effort high
uniquify
# compile the design
compile_ultra -area_high_effort_script
#compile_ultra -timing_high_effort_script
#compile_ultra
# Now that the compile is complete report on the results
report_area
report_timing
report_power
############################### begin: renaming section
# remove the following renaming section when not needed
# define the name rules for rename
define_name_rules verilog -remove_port_bus
define_name_rules verilog -remove_internal_net_bus
# name rule for nets
define_name_rules verilog -type net -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9 N" \
-replacement_char "_" \
-prefix "n"
# name rule for cells
define_name_rules verilog -type cell -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9" \
-replacement_char "_" \
-prefix "u"
# name rule for ports
define_name_rules verilog -type port -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9" \
-replacement_char "_" \
-prefix "p"
# change names of variables
change_names -rule verilog -hierarchy
################################ end: renaming section
# Write out the design
write -f verilog TOP1553 -output TOP1553_syn.v
remove_design -all
exit