紧急贴！vhdl转成原理图的时候就会报错“,不支持这个端口输入的类型”，

这是一个数字时钟寄存器程序，我按照书上的程序输入到Quartus2 9中，编译通过了，但是在生成元器件时出现这个错误，Error (10017): Can't create symbol/include/instantiation/component file for entity "REG" because port "NEW_ALARM_TIME" has an unsupported type。Error (10017): Can't create symbol/include/instantiation/component file for entity "REG" because port "ALARM_TIME" has an unsupported type。以下是程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE P_ALARM IS
  SUBTYPE T_DIGITAL IS INTEGER RANGE 0 TO 9;
  SUBTYPE T_SHORT IS INTEGER RANGE 0 TO 65535;
  TYPE T_CLOCK_TIME IS ARRAY (6 DOWNTO 0)OF T_DIGITAL;
   TYPE T_DISPLAY IS ARRAY (6 DOWNTO 0)OF T_DIGITAL;
END PACKAGE P_ALARM;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY REG IS
  PORT(NEW_ALARM_TIME:IN T_CLOCK_TIME;
       LOAD_NEW_A:IN STD_LOGIC;
       CLK:IN STD_LOGIC;
       RESET:IN STD_LOGIC;
      ALARM_TIME:OUT T_CLOCK_TIME);
END ENTITY REG;
ARCHITECTURE ART OF REG IS
  BEGIN
  PROCESS(CLK,RESET) IS
   BEGIN
IF RESET='1' THEN
     ALARM_TIME(0)<=0;
     ALARM_TIME(1)<=0;
     ALARM_TIME(2)<=0;
     ALARM_TIME(3)<=0;
     ALARM_TIME(4)<=0;
     ALARM_TIME(5)<=0;
    ELSE
IF RISING_EDGE(CLK) THEN
   IF LOAD_NEW_A='1' THEN
      ALARM_TIME<=NEW_ALARM_TIME;
      END IF;
    END IF;
    END IF;
   END PROCESS;
END ARCHITECTURE ART;
应该把T_CLOCK_TIME 改成什么类型才能通过，求大神指点！紧急贴，非常紧急！

T-CLOCK_TIME 是你自定义的数据类型。
要么你是没把包含该数据类型的定义文件没有include进去，要么你定义有错。