请教FPGA route不正常的原因
时间：10-02
整理：3721RD
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请教下面的route时间，太长，占78%，可能是什么导致的?
Paths for end point u2_scaler/u_sram5_tp/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36_X4Y25.DIADI1), 2226 paths -------------------------------------------------------------------------------- Slack (setup path): -4.266 ns (requirement - (data path - clock path skew + uncertainty)) Source: u2_scaler/dut/u2_filter1_R/OOo_6 (FF) Destination: u2_scaler/u_sram5_tp/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAM) Requirement: 6.600ns Data Path Delay: 10.831ns (Levels of Logic = 11) Clock Path Skew: 0.000ns Source Clock: dclk_150m rising at 0.000ns Destination Clock: dclk_150m rising at 6.600ns Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns ---------------------------------------------------- --------------------------- Total 10.831ns (3.053ns logic, 7.778ns route) (28.2% logic, 71.8% route)
Paths for end point u2_scaler/u_sram5_tp/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36_X4Y25.DIADI1), 2226 paths -------------------------------------------------------------------------------- Slack (setup path): -4.266 ns (requirement - (data path - clock path skew + uncertainty)) Source: u2_scaler/dut/u2_filter1_R/OOo_6 (FF) Destination: u2_scaler/u_sram5_tp/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAM) Requirement: 6.600ns Data Path Delay: 10.831ns (Levels of Logic = 11) Clock Path Skew: 0.000ns Source Clock: dclk_150m rising at 0.000ns Destination Clock: dclk_150m rising at 6.600ns Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns ---------------------------------------------------- --------------------------- Total 10.831ns (3.053ns logic, 7.778ns route) (28.2% logic, 71.8% route)
如何解决route太长的问题呢?
route、place本来就占真个过程的绝大部门时间，如果时间确实达到受不了的地步，考虑一下问题
1、设计相对复杂，优化部门复杂模块
2、约束太严，不断route使满足约束
非常感谢，我的问题是critical path中的route有7ns，导致时序过不了，而不是综合时间太长。现在我通过手动place，可以缩小route所需的时间，使设计可以跑120M。