Spartan6使用DCM不能通过MAP
时间：10-02
整理：3721RD
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一项目，使用了XILINX FPGA，DCM做倍频用。原来使用Spartan 3S400时没有问题。
现改用Spartan6 LX45，使用ISE P&R时出错：
ERRORlace:1355 - Component < u_clock/hf_clk_iso > is driven by DCM or PLL
component < dcm_pll48m/DCM_SP > placed at < DCM_X0Y1 >. This requires the
load component to be range constrained to CLOCKREGION_X0Y0 or
CLOCKREGION_X1Y0. Placer was not able to apply this range constraint because
component < u_clock/hf_clk_iso > has a LOC constraint or area group in a
different clock region. Please check whether the user constraints and remove
any conflicting LOCs or area groups. Note that the loads of a DCM/PLL must be
constrained to the two adjacent clock regions to the DCM/PLL.
如果删除DCM，将原来接DCM输出引脚的时钟直接连至FPGA的GCLK输入，则没有问题。
上面的提示不是很明白，似乎是要将和DCM有关的电路放限制在某块区域?
请高手指点一下，Spartan 6中使用DCM有什么注意的地方?上述问题要怎样解决?
现改用Spartan6 LX45，使用ISE P&R时出错：
ERRORlace:1355 - Component < u_clock/hf_clk_iso > is driven by DCM or PLL
component < dcm_pll48m/DCM_SP > placed at < DCM_X0Y1 >. This requires the
load component to be range constrained to CLOCKREGION_X0Y0 or
CLOCKREGION_X1Y0. Placer was not able to apply this range constraint because
component < u_clock/hf_clk_iso > has a LOC constraint or area group in a
different clock region. Please check whether the user constraints and remove
any conflicting LOCs or area groups. Note that the loads of a DCM/PLL must be
constrained to the two adjacent clock regions to the DCM/PLL.
如果删除DCM，将原来接DCM输出引脚的时钟直接连至FPGA的GCLK输入，则没有问题。
上面的提示不是很明白，似乎是要将和DCM有关的电路放限制在某块区域?
请高手指点一下，Spartan 6中使用DCM有什么注意的地方?上述问题要怎样解决?
引脚的时钟直接
问题已解决，是因为两个DCM串联的原因。
两个DCM串联需要注意些什么呢?