verilog 书写风格讨论

1.
always @(posedge clk or negedge rst_n)
begin
  if (！rst_n) begin
    r_c <= 2'd0;
    r_a <= #1 2'd0;
  end
  else begin
    r_a <= #1 r_b;
    r_c <= #1 r_b;
  end
end
在仿真和综合时，这两种写法有什么不同?
Is there some difference in simulation and synthsis?
2.
parameter BIT_WIDTH = 8;
parameter BUFF_LENGTH = 16;
input [BIT_WIDTH-1:0] i_data;
reg [BIT_WIDTH-1:0]s_data_buff[BUFF_LENGTH-1:0];
integer i;
2.1
always @(posedge clk or negedge rst_n)
if (！rst_n) begin
  for(i=0; i< BUFF_LENGTH; i=i+1)s_data_buff[i] <= #1 {BIT_WIDTH{1'd0}};
end
else begin
  s_data_buff[0] <= #1 i_data;
  for(i=0; i< BUFF_LENGTH-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff[i];
end
2.2
wire [3:0] w_buff_length;//0--15
always @(posedge clk or negedge rst_n)
if (！rst_n) begin
  for(i=0; i< w_buff_length; i=i+1)s_data_buff[i] <= #1 {BIT_WIDTH{1'd0}};
end
else begin
  s_data_buff[0] <= #1 i_data;
  for(i=0; i< w_buff_length-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff[i];
end
这两种写法都可以使用吗?
Are the two styles both good ?
3.
parameter DEPTH = 10;
parameter WIDTH = 8;
generate
genvar i;
for ( i = 0;i <DEPTH;i = i + 1 ) begin:data_gen
reg [WIDTH - 1:0] data;
if ( i == 0 ) begin
    always @ ( posedge clk,negedge resetn )
    if ( ！resetn ) begin
        data <= { ( DEPTH ) {1'b0}};
    end
    else begin
        if ( conditiona) data_gen[i].data <= { ( DEPTH ) {1'b0}};
        else if ( conditionb) data_gen[i].data <= din;
        else if ( conditionc ) data_gen[i].data <= data_gen[i + 1].data;
        else data_gen[i].data <= data_gen[i].data;
    end
end
else if ( i < DEPTH - 1 ) begin
    always @ ( posedge clk,negedge resetn )
    if ( ！resetn ) begin
        data <= { ( DEPTH ) {1'b0}};
    end
    else begin
        if ( conditiona) data_gen[i].data <= din;
        else if ( conditionb ) data_gen[i].data <= data_gen[i + 1].data;
        else data_gen[i].data <= data_gen[i].data;
    end
end
else begin
    always @ ( posedge clk,negedge resetn )
    if ( ！resetn ) begin
        data <= { ( DEPTH ) {1'b0}};
    end
    else begin
        if ( conditiona ) data_gen[i].data <= din;
        else data_gen[i].data <= data_gen[i].data;
    end
end
end
endgenerate
有人经常使用generate语法吗?
Is there anybody usually use generate syntax?