synplify在综合的时候出现的问题

在synplify综合的时候显示有一个错误三个警告。
但是在synthesis check中出现的是这些：
@W: CL118 :"F:\exe\traffic.v":93:4:93:7|Latch generated from always block for signal light_d[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"F:\exe\traffic.v":93:4:93:7|Latch generated from always block for signal light_c[2:0], probably caused by a missing assignment in an if or case stmt
@N: CL177 :"F:\exe\traffic.v":93:4:93:7|Sharing sequential element light_c.
@N: CL177 :"F:\exe\traffic.v":93:4:93:7|Sharing sequential element light_c.
@W: CL118 :"F:\exe\traffic.v":93:4:93:7|Latch generated from always block for signal light_b[2:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"F:\exe\traffic.v":93:4:93:7|Latch generated from always block for signal light_a[2:0], probably caused by a missing assignment in an if or case stmt
@N: CL177 :"F:\exe\traffic.v":93:4:93:7|Sharing sequential element light_a.
@N: CL177 :"F:\exe\traffic.v":93:4:93:7|Sharing sequential element light_a.
@W: CL118 :"F:\exe\traffic.v":27:2:27:3|Latch generated from always block for signal urg_r[1:0], probably caused by a missing assignment in an if or case stmt
并没有@E。 同时，我在我代码的所有case里面都有default，所有的if后面都根由else语句。不知道要怎么改了。