自己写的xilinx spartan-3上verilogHDL设计的四位十进制数加减乘除计算器，求指教。

verilogHDL设计的四位十进制数加减乘除计算器，请发到zjuwh@sina.cn，要求如下：
Implement a decimal calculator,operate addition, subtraction, multiplication and division for two 16 bits numbers and display the results in 7-segment LED display.Using decimal numbers as the inputs/outputs. Each input is 4 decimals (16 bits).Display an error message (ERR)when the divisor is 0.Please make your own user interact design to control the calculation operation, to display the operation results,and provide the clear user manual. Build Behavioral Simulation and submit the simulation results.
平台是xilinx ISE开发板spartan-3，自己写了verilogHDL代码和ucf文件，求指教。
module caculator(clk, btn_in,sw, led,digit_anode, segment);
input  clk;
input  [3:0] sw;
input [3:0] btn_in;
output [3:0] digit_anode;
output [ 7:0] segment;
wire clk_1ms;
wire [3:0] btn_in;
wire [3:0] digit_anode;
wire [7:0] segment;
reg [15:0] disp_num=16’b0;
wire [3:0] btn_out;
reg [8:1] A,B;
initial begin
  A<=8'b0000_0000;
  B<=8'b0000_0000;
end
Timer_1ms I2 (clk,clk_1ms);
anti_jitter I1 (clk,clk_1ms,btn_in,btn_out);
always@(posedge btn_out[0]) begin B[ 4: 1]<=B[ 4: 1] + 4'd1; if(B[4:1]>4’d9) B[4:1]<=4’b0000; end
always@(posedge btn_out[1]) begin B[8:5]<=B[8: 5] + 4'd1; if(B[8:5])>4’d9) B[8:5]<=4’b0000; end
always@(posedge btn_out[2]) begin A[ 4: 1]<=A[ 4: 1] + 4'd1; if(A[4:1]>4’d9) A[4:1]<=4’b0000; end
always@(posedge btn_out[3]) begin A[8:5]<=A[8:5]+4'd1; if(A[8:5]>4’d9)
A[8:5]<=4’b0000; end
always@(sw[3])begin A<=8’b00000000;B<=8’b00000000;end
cal ca(A,B,sw[2:0],disp_num);
display     DISPLAY_0(clk, disp_num,digit_anode, segment);
end
endmodule
module cal (a,b,sw,result);
input [8:1] a;
input [8:1] b;
input [2:0] sw;
output [15:0] result;
reg [15:0] result;
reg [15:0] t=16’b0;
always@(sw[2:0] or a or b)begin
case(sw[2:0])
000:begin result={a[8:1],b[8:1]};end
001:begin t=a+b;tobcd(t,result);end
010:begin if(a<b)begin t=b-a;tobcd(t,result);result={4’b1010,result[11:0]};end
else begin t=a-b;tobcd(t,result); end end
011:begin t=a*b;tobcd(t,result); end
100:begin if(b！=0)begin t=a/b; tobcd(t,result);end else result=12’b101111001100;end
default: result=0;
endcase
end
endmodule
module tobcd(in,result);
input [15:0] in;
output [15:0] result;
reg [15:0] result;
result[3:0]=in%4’d10;
result[7:4]=(in/4’d10)%4’d10;
result[11:8]=(in/4’d100)%4’d10;
result[15:12]=(in/4’d1000)%4’d10;
endmodule
module display(clk,digit,node,segment);
input wire        clk;
input wire [15:0] digit;
output reg [ 3:0] node;
output reg [ 7:0] segment;
reg [3:0]  code  =  4'b0;
reg [15:0] count = 16'b0;
always @(posedge clk)begin
case (count[15:14])
        2'b00 : begin
            node <= 4'b1110;
            code <= digit[3:0];
            end
        2'b01 : begin
            node <= 4'b1101;
            code <= digit[7:4];
            end
        2'b10 : begin
            node <= 4'b1011;
            code <= digit[11:8];
                    end
        2'b11 : begin
            node <= 4'b0111;
            code <= digit[15:12];
            end
endcase
    case (code)
        4'b0000: segment <= 8'b11000000;
        4'b0001: segment <= 8'b11111001;
        4'b0010: segment <= 8'b10100100;
        4'b0011: segment <= 8'b10110000;
        4'b0100: segment <= 8'b10011001;
        4'b0101: segment <= 8'b10010010;
        4'b0110: segment <= 8'b10000010;
        4'b0111: segment <= 8'b11111000;
        4'b1000: segment <= 8'b10000000;
        4'b1001: segment <= 8'b10010000;
                4’b1010: segment <= 8’b10111111;
                4’b1011: segment <= 8’b10000110;
                4’b1100: segment <= 8’b10001000;
        default: segment <= 8'b11111111;
endcase
    count <= count + 1;
end
endmodule
module anti_jitter(clk, clk_1ms, btn, btn_out);
input                                        clk;
input                                        clk_1ms;
input                [3:0]                btn;
output        [3:0]                btn_out;
wire                                        clk, clk_1ms;
wire                [3:0]                btn;
reg                [3:0]                btn_out;
reg                [3:0]                cnt_aj;
reg                [3:0]                btn_old;
initial begin
        cnt_aj <= 0;
        btn_out <= 4'b0000;
        btn_old <= 4'b0000;
end
always @(posedge clk) begin
        if (btn ！= btn_old) begin
                cnt_aj <= 4'b0000;
                btn_old <= btn;
        end
        else begin
                if (clk_1ms) begin
                        if (cnt_aj == 4'b1111) begin
                                cnt_aj <= 4'b0000;
                                btn_out <= btn;
                        end
                        cnt_aj <= cnt_aj + 1;
                end
        end
end
endmodule
module Timer_1ms(clk, clk_1ms);                        //1ms timer
input                                        clk;
output                                clk_1ms;
wire                                        clk;
reg                                        clk_1ms;
reg                [15:0]        cnt;
initial begin
        cnt [15:0] <= 0;
end
always @(posedge clk) begin
        if (cnt >= 49999) begin
                cnt <= 0;
                clk_1ms <= 1;
        end
        else begin
                cnt <= cnt + 1;
                clk_1ms <= 0;
        end
end
endmodule
UCF:
Net "clk" loc = "T9";
net "segment[0]" loc = "E14";
net "segment[1]" loc = "G13";
net "segment[2]" loc = "N15";
net "segment[3]" loc = "P15";
net "segment[4]" loc = "R16";
net "segment[5]" loc = "F13";
net "segment[6]" loc = "N16";
net "segment[7]" loc = "P16";
net "digit_anode[0]" loc = "D14";
net "digit_anode[1]" loc = "G14";
net "digit_anode[2]" loc = "F14";
net "digit_anode[3]" loc = "E13";
net "btn_in[0]" loc = "L14";
net "btn_in[1]" loc = "L13";
net "btn_in[2]" loc = "M14";
net "btn_in[3]" loc = "M13";
net "sw[0]" loc = "F12";
net "sw[1]" loc = "G12";
net "sw[2]" loc = "H14";
net "sw[3]" loc = "H13";

上述代码前半部分改为：
module caculator(clk, btn_in,sw, led,digit_anode, segment);
input  clk;
input  [3:0] sw;
input [3:0] btn_in;
output [3:0] digit_anode;
output [ 7:0] segment;
wire clk_1ms;
wire [3:0] btn_in;
wire [3:0] digit_anode;
wire [7:0] segment;
reg [15:0] disp_num=16’b0;
wire [3:0] btn_out;
reg [7:0] A,B;
initial begin
   A<=8'b0000_0000;
   B<=8'b0000_0000;
end
Timer_1ms I2 (clk,clk_1ms);
anti_jitter I1 (clk,clk_1ms,btn_in,btn_out);
always@(posedge btn_out[0]) begin B[3:0]<=B[3:0] + 4'd1; if(B[3:0]>4’d9) B[3:0]<=4’b0000; end
always@(posedge btn_out[1]) begin B[7:4]<=B[7:4] + 4'd1; if(B[7:4])>4’d9) B[7:4]<=4’b0000; end
always@(posedge btn_out[2]) begin A[3:0]<=A[3:0] + 4'd1; if(A[3:0]>4’d9) A[3:0]<=4’b0000; end
always@(posedge btn_out[3]) begin A[7:4]<=A[7:4]+4'd1; if(A[7:4]>4’d9)
A[7:4]<=4’b0000; end
always@(negedge sw[3])begin A<=8’b00000000;B<=8’b00000000;end
cal ca(A,B,sw[2:0],disp_num);
display     DISPLAY_0(clk, disp_num,digit_anode, segment);
end
endmodule
module cal (A,B,sw,result);
input [7:0] A;
input [7:0] B;
input [2:0] sw;
output [15:0] result;
reg [15:0] result;
reg [15:0] t;
reg [7:0] a,b;
a=A[7:4]*4’d10+A[3:0]; b=B[7:4]*4’d10+B[3:0];result=0;
always@(sw[2:0] or a or b)begin t=0;
case(sw[2:0])
  000:begin result={A,B};end
  001:begin t=a+b;tobcd(t,result);end
  010:begin if(a<b)begin t=b-a;tobcd(t,result);result={8’bxxxx1010,result[7:0]};end
else begin t=a-b;tobcd(t,result); end end
011:begin t=a*b;tobcd(t,result); end
  100:begin if(b！=0)begin t=a/b; tobcd(t,result);end else result=16’bxxxx101111001100;end
  default: result=0;
  endcase
end
endmodule