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利用块RAM实现数据延迟的一些问题

时间：10-02 整理：3721RD 点击：
这个是利用块RAM实现a、b两路数据延迟，数据位宽都为32，其中a路延迟16个数据周期，b路延迟8个数据周期，代码如下：

  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date:    20:51:45 12/15/2013
  7. // Design Name:
  8. // Module Name:    bram_delay
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module bram_delay(
  22.     input wire clk,
  23.          input wire rst_n,
  24.          input wire[31:0] a_in,
  25.          input wire[31:0] b_in,
  26.          output reg[31:0] a_delay,
  27.          output reg[31:0] b_delay);
  28. /*************************************************************************/   
  29.          parameter DEL = 1;
  30. /*************************************************************************/
  31.     wire[5:0] a_addr;
  32.     wire[5:0] b_addr;
  33.          wire[31:0] douta;
  34.          wire[31:0] doutb;
  35.          reg[5:0] a_addr1 = 6'd0;
  36.          reg[5:0] a_addr2 = 6'd0;
  37.          reg[5:0] b_addr1 = 6'd32;
  38.          reg[5:0] b_addr2 = 6'd32;
  39.          reg wea = 1'b0;
  40.          reg web = 1'b0;
  41.          reg flag = 1'b0;
  42.          
  43. /**************************************************************************/
  44.     always @ ( posedge clk)
  45.              begin
  46.                       if( rst_n == 1'b0 )
  47.                                     begin
  48.                                              a_delay <= 32'b0;
  49.                                                   b_delay <= 32'b0;
  50.                                          end
  51.                                 else begin
  52.                       flag <= #DEL ！flag;
  53.                                 if( flag == 1'b1)
  54.                                     begin
  55.                                              a_delay <= #DEL a_delay;
  56.                                                   b_delay <= #DEL b_delay;
  57.                                                   wea <= #DEL 1'b1;
  58.                                                   web <= #DEL 1'b1;
  59.                                                   a_addr2 <= #DEL a_addr2;
  60.                                                   b_addr2 <= #DEL b_addr2;
  61.                                                   if( a_addr1 == 6'd31)
  62.                                                       a_addr1 <= #DEL 6'd0;
  63.                                                   else
  64.                                                       a_addr1 <= #DEL a_addr1 + 6'b1;
  65.                                                   if( b_addr1 == 6'd63)
  66.                                                       b_addr1 <= #DEL 6'd0;
  67.                                                   else
  68.                                                       b_addr1 <= #DEL b_addr1 + 6'b1;
  69.                 end
  70.             else
  71.                           begin
  72.                               a_delay <= #DEL douta;
  73.                                         b_delay <= #DEL doutb;
  74.                                         wea <= #DEL 1'b0;
  75.                                         web <= #DEL 1'b0;
  76.                                         a_addr1 <= #DEL a_addr1;
  77.                                         b_addr1 <= #DEL b_addr1;
  78.                                         if( a_addr1 <= 6'd15)
  79.                                             a_addr2 <= #DEL a_addr1 + 6'd16;
  80.                                         else
  81.                                             a_addr2 <= #DEL a_addr1 - 6'd16;
  82.                                         if( b_addr1 <= 6'd39)
  83.                                             b_addr2 <= #DEL b_addr1 + 6'd24;
  84.                                         else
  85.                                             b_addr2 <= #DEL b_addr1 - 6'd8;
  86.                 end
  87.                                 end
  88.         end
  89. /*************************************************************************/

  91.     assign a_addr = ！flag ? a_addr1 : a_addr2;
  92.          assign b_addr = ！flag ? b_addr1 : b_addr2;
  93. /**************************************************************************/
  94.   bram_16 dut (
  95.   .clka(clk), // input clka
  96.   .wea(wea), // input [0 : 0] wea
  97.   .addra(a_addr), // input [5 : 0] addra
  98.   .dina(a_in), // input [15 : 0] dina
  99.   .douta(douta), // output [15 : 0] douta
  100.   .clkb(clk), // input clkb
  101.   .web(web), // input [0 : 0] web
  102.   .addrb(b_addr), // input [5 : 0] addrb
  103.   .dinb(b_in), // input [15 : 0] dinb
  104.   .doutb(doutb) // output [15 : 0] doutb
  105.    );                     

  107. endmodule

复制代码



这个程序功能能够实现，仿真结果也正确，但是却出现瑕疵，综合出现结果如下：

  1. WARNING:Xst:916 - "bram_delay.v" line 52: Delay is ignored for synthesis.
  2. WARNING:Xst:916 - "bram_delay.v" line 55: Delay is ignored for synthesis.
  3. WARNING:Xst:916 - "bram_delay.v" line 56: Delay is ignored for synthesis.
  4. WARNING:Xst:916 - "bram_delay.v" line 57: Delay is ignored for synthesis.
  5. WARNING:Xst:916 - "bram_delay.v" line 58: Delay is ignored for synthesis.
  6. WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
  7. WARNING:Xst:2211 - "ipcore_dir/bram_16.v" line 94: Instantiating black box module <bram_16>.
  8. WARNING:Xst:647 - Input <b_in<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  9. WARNING:Xst:647 - Input <a_in<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  10. WARNING:Xst:1710 - FF/Latch <b_delay_31> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  11. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_30> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  12. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_29> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  13. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_28> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  14. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_27> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  15. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_26> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  16. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_25> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  17. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_24> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  18. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_23> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  19. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_22> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  20. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_21> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  21. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_20> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  22. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_19> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  23. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_18> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  24. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_17> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  25. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_16> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  26. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_31> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  27. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_30> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  28. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_29> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  29. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_28> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  30. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_27> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  31. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_26> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  32. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_25> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  33. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_24> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  34. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_23> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  35. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_22> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  36. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_21> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  37. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_20> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  38. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_19> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  39. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_18> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  40. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_17> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  41. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_16> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  42. WARNING:Xst:2404 -  FFs/Latches <b_delay<31:16>> (without init value) have a constant value of 0 in block <bram_delay>.
  43. WARNING:Xst:2404 -  FFs/Latches <a_delay<31:16>> (without init value) have a constant value of 0 in block <bram_delay>.

复制代码



对于a_delay和b_delay都已经初始化了的，为什么还出现这个问题?仿真图如下：





望各位坛友支支招，在此谢谢了！

如果只是延时32的话，完全可以用移位寄存器(分布式RAM)实现，用BRAM浪费了


如果考虑到优化的话，确实用分布式RAM比较好，但问题是为什么会出现上述问题?

看这样子是没有复位，小编把rst_n低电平的时间弄长一点。


刚开始在复位时，我是写有延时的，结果还是一样，所以后来我就直接删除了！

数据要先赋值，然后读取啊，你开始仿真，还没有把RAM整个初始化完，那写一段地址的数据进去，读另一段地址的数据出来，那段还没初始化过，自然会是z了。
flag怎么激励的?
按你的写法，flag应是渐段式激励吧?写1后再写0，然后等延迟若干后地址的数据输出。
另外，对a, b路的关系觉得很诡异，按你的想法，a, b路是关系平等的两路数据，只是分别延迟不同地址而已吧?那你用个真双口是为了什么?真双口的数据对A口和B口来说，内容是共享的，那岂不是a, b路数据相互冲突了?


你说的应该没错，应该就是初始化时间不够造成的。我知道真双口RAM的内容是共享的，所以我固定前段地址（0—31）只能写a数据，后段（32—63）数据只能写b数据，而且输出地址也是有设置了的，故我觉得虽然共享，但它们的数据是不会矛盾的，不会有冲突！不知这样是否妥当?



有这样处理自然没问题，不会冲突就好，你还可以直接用两个单口RAM啊，二者在RAM的使用面积上是一致的


是啊，考虑到数据方面，最后还是改成分布式的了，利用器件原语，节省资源。总之，谢谢了！

受教了，谢谢

实现数据延迟最好的方式是用fifo。 你自己用ram外加控制逻辑，如果控制逻辑写的不好很容易出问题。xilinx有源码的fifo好用

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