请问always@(*)是什么意思，任何事件触发？

Verilog 标准2001中开始可以这样表示的，你可以去看看标准
9.7.5 Implicit event_expression list The event_expression list of an event control is a common source of bugs in RTL simulations. Users tend to forget to add some of the nets or variables read in the timing control statement. This is often found when comparing RTL and gate level versions of a design. The implicit event_expression, @*, is a convenient shorthand that eliminates these problems by adding all nets and variables which are read by the statement (which can be a statement group) of a procedural_timing_control_statement to the event_expression.
All net and variable identifiers which appear in the statement will be automatically added to the event expression with these exceptions: Identifiers which only appear in wait or event expressions.
Identifiers which only appear as a hierarchical_reg_identifier in the reg_lvalue of the left hand side of assignments.
Nets and variables which appear on the right hand side of assignments, in function and task calls, or case and conditional expressions shall all be included by these rules.
Examples:
Example 1 always @(*) // equivalent to @(a or b or c or d or f) y = (a & b) | (c & d) | myfunction(f);
Example 2 always @* begin // equivalent to @(a or b or c or d or tmp1 or tmp2) tmp1 = a & b; tmp2 = c & d; y = tmp1 | tmp2; end
Example 3 always @* begin // equivalent to @(b) @(i) kid = b; // i is not added to @* end
Example 4 always @* begin // equivalent to @(a or b or c or d) x = a ^ b; @* // equivalent to @(c or d) x = c ^ d; end

ise中不是完全支持

always @(*)
* 信號若是有變化，則會執行 always 區塊裡面的敘述。
一般來說，通常就是會合成組合邏輯 (Combinational Logic).
台灣式中文，希望你看得懂。

z什么啊

all the signals can trigged this process

Verilog2001的新用法

always模块中的所有赋值信号发生变化,都会触发模块重新计算.
电平敏感的纯组合逻辑.

有些工具是不支持的，还是老老实实的写全敏感列表吧。

好东西，顶啊

组合逻辑的所有信号变化都触发
2001的语法标准

在FPGA设计中有问题，把输入信号全列进去的写法比较好。

very good

复杂功能还是用VHDL比较清晰

*是指在你的always块儿内所有的输入信号都列到了敏感列表中。