ise+synplify的问题

想请教诸位一个综合的问题。曾做过一个工程，运行正常。现在将该工程的代码作为另一新工程的一个模块，但是在新工程中，这个模块综合不出来。在translate 里报错是该模块由于管脚拼写错，缺少网表文件，该器件不支持的错误，在synplify里看综合的rtl图是一个黑框，而且无法点击进入下一级的子模块，感觉像一个黑盒。

报error的log呢，贴出来。

   这就是一个黑盒，你要搞清楚这个黑盒IP的功能，在新版里面重新生成一个一样的IP。

这是在实现时报的错：
ERROR  NgdBuild:76 - File "E:\xx\leon_net_project\_ngo\leon_ctrl.ngo" cannot be merged into block "leon_ctrl_00" (TYPE="leon_ctrl") because one or more pins on the block, including pin "pio_out_p", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.   ERROR  NgdBuild:604 - logical block 'leon_ctrl_00' with type 'leon_ctrl' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'leon_ctrl' is not supported in target 'virtex5'.

这是ISE实现时报出的错
ERROR  NgdBuild:76 - File "E:\xx\leon_net_project\_ngo\leon_ctrl.ngo" cannot be merged into block "leon_ctrl_00" (TYPE="leon_ctrl") because one or more pins on the block, including pin "pio_out_p", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.   ERROR  NgdBuild:604 - logical block 'leon_ctrl_00' with type 'leon_ctrl' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'leon_ctrl' is not supported in target 'virtex5'.

   这个模块真不是一个黑盒，所有添加到工程里的都是代码文件。只是原本这个模块是用VHDL写的，而这次顶层我是用verilog写的，后来又把顶层用VHDL重新写了一遍，添加到工程里，就没出现过上述现象，具体原因真不知道是为什么。

ISE实现时报的错
ERROR  NgdBuild:76 - File "E:\xx\leon_net_project\_ngo\leon_ctrl.ngo" cannot be merged into block "leon_ctrl_00" (TYPE="leon_ctrl") because one or more pins on the block, including pin "pio_out_p", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.   
ERROR  NgdBuild:604 - logical block 'leon_ctrl_00' with type 'leon_ctrl' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'leon_ctrl' is not supported in target 'virtex5'.

NGO文件不用添加到synplify里面去给，直接在ISE下布线即可。
你可以自己写了个黑盒文件，把ngo文件里面的端口列一下即可，然后把它加到synplify的综合工程里面去。

1、比如你以前的工程顶层叫“block_top”，那你在ise里综合下，工程默认目录得到一个ngc文件，block_top.ngc，为网表文件。
2、移除synplify里block_top.v，及它下面的所有子v文件，复制一个block_top.v，做成一个黑盒v文件，就是只保留模块名、端口、参数，其余全部删掉，例如 ：
module block_top#(paramter XX = XX ......) (input  xx, ....);
endmodule
将该黑盒子文件添加到synplify中。
3、synplify综合，综合完，打开rtl图，找到被综合成黑色框的block_top模块，记下被综合后的名字，一般来说，模块框下面是综合前名字，模块框顶部是综合后名字，把之前用ise综合的block_top.ngc也改为这个综合后的名字（如果名字一样则不用改）
4、把synplify得到的edf后者edif文件加入ise工程，还有你的约束文件。
5、右键ise的translate，在“宏”一栏里，添加你的ngc文件的路径，就是添加你改名后的bock_top.ngc所在文件夹的路径，设置好后，点击OK。
6、编译，应该是成功的。

管脚有错误。一般是空文件和edf之间有差异

   整个工程全都是代码文件，只是原本这个模块是用VHDL写的，而这次顶层我是用verilog写的，后来又把顶层用VHDL重新写了一遍，添加到工程里，就完全正常