求助 用quartus调用modelsim时候出现“vsimk.exe停止工作”

modeslim 用的是10.1a se quartus的版本是11.0sp1
然后在modeslim中出现的信息提示如下：
“  -- Compiling entity ddr2_wrapper_mem_model
# -- Compiling architecture europa of ddr2_wrapper_mem_model
#
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L arriaii_hssi -L arriaii_pcie_hip -L arriaii -L rtl_work -L work -voptargs="+acc" ddr2_wrapper_example_top_tb
# vsim -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L arriaii_hssi -L arriaii_pcie_hip -L arriaii -L rtl_work -L work -voptargs=\"+acc\" -t 1ps ddr2_wrapper_example_top_tb
# ** Note: (vsim-3812) Design is being optimized...
#
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./ddr_sim_run_msim_rtl_vhdl.do PAUSED at line 68
”
我查看了下ddr_sim_run_msim_rtl_vhdl.do PAUSED at line 68的对应内容是：
“vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L arriaii_hssi -L arriaii_pcie_hip -L arriaii -L rtl_work -L work -voptargs="+acc" ddr2_wrapper_example_top_tb
”
看论坛里有人发过这个问题虽然查看的人很多但是没有解答。
求大牛蒡解答

你试着直接启动ModelSim仿真器进行仿真，并且仿真命令改为
vsim -novopt -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L arriaii_hssi -L arriaii_pcie_hip -L arriaii -L rtl_work -L work ddr2_wrapper_example_top_tb

   liu 工谢谢 你的提示， 按照您的回复我是这么做的 不知对不对，直接在modelsim change Directory 到ddr_sim_run_msim_rtl_vhdl.do所在的目录 在transcript 窗口中运行do ddr_sim_run_msim_rtl_vhdl.do命令虽然提示结果和之前的有点不一样但不是还是过不去。信息如下：会不会是modelsim的版本太高了 在quartus11.0调用modelsim 10.1a的时候出了问题呢?（我用的是VHDL语言）
# Refreshing C:\Users\212418275\Desktop\work\sim\quartus_sim\simulation\modelsim\rtl_work.alt_mem_ddrx_ecc_decoder_32_decode
# Loading work.alt_mem_ddrx_ecc_decoder_32_decode
# ** Error: (vsim-10000) C:/Users/212418275/Desktop/work/sim/quartus_sim/dram_if/ddr2_wrapper/alt_mem_ddrx_buffer.v(96): Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.address_aclr_a.
#
#         Region: /ddr2_wrapper_example_top_tb/dut/ddr2_wrapper_inst/ddr2_wrapper_controller_phy_inst/ddr2_wrapper_alt_mem_ddrx_controller_top_inst/controller_inst/controller_inst/rdata_path_inst/gen_rdata_return_inorder/genblk1/in_order_buffer_inst
# ** Error: (vsim-10000) C:/Users/212418275/Desktop/work/sim/quartus_sim/dram_if/ddr2_wrapper/alt_mem_ddrx_buffer.v(97): Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.address_aclr_b.
#
#         Region: /ddr2_wrapper_example_top_tb/dut/ddr2_wrapper_inst/ddr2_wrapper_controller_phy_inst/ddr2_wrapper_alt_mem_ddrx_controller_top_inst/controller_inst/controller_inst/rdata_path_inst/gen_rdata_return_inorder/genblk1/in_order_buffer_inst
# ** Error: (vsim-10000) C:/Users/212418275/Desktop/work/sim/quartus_sim/dram_if/ddr2_wrapper/alt_mem_ddrx_buffer.v(98): Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.address_reg_b.
#
#         Region: /ddr2_wrapper_example_top_tb/dut/ddr2_wrapper_inst/ddr2_wrapper_controller_phy_inst/ddr2_wrapper_alt_mem_ddrx_controller_top_inst/controller_inst/controller_inst/rdata_path_inst/gen_rdata_return_inorder/genblk1/in_order_buffer_inst
# ** Error: (vsim-10000) C:/Users/212418275/Desktop/work/sim/quartus_sim/dram_if/ddr2_wrapper/alt_mem_ddrx_buffer.v(99): Unresolved defparam reference to 'altsyncram_component' in altsyncram_component.indata_aclr_a.
#
................................
.................................
.................................
# Loading work.ddr2_wrapper_mem_model_ram_module(europa)
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./ddr_sim_run_msim_rtl_vhdl.do PAUSED at line 68

VHDL仿真里面怎么出现了alt_mem_ddrx_buffer.v的Verilog代码?